From Model to Silicon: Proven Techniques to Verify Implementation of Algorithms in ICs
| Start Time | End Time |
|---|---|
| 25 Sep 2025, 12:00 PM EDT | 25 Sep 2025, 1:00 PM EDT |
Overview
Integrated circuit design teams rely on Cadence Xcelium, Synopsys VCS, or Siemens Questa in their production verification environments. The signal processing and control algorithms implemented in these devices are typically developed using MATLAB and Simulink before being implemented in RTL. In this webinar, we will demonstrate verification methods used by system designers, verification engineers, and other team members to connect MATLAB and Simulink to functional verification.
- Algorithm verification: Utilize MATLAB and Simulink models as testbenches with RTL for the Device Under Test (DUT).
- Behavioral modeling for RTL designs: Use MATLAB to add behavioral models to HDL designs during RTL development.
- Verification component generation: Learn how to generate verification components from MATLAB and Simulink models for verification in production environments.
- RTL verification workflows: Explore workflows for verifying Register-Transfer Level (RTL) designs using HDL generation from MATLAB and Simulink.
About the Presenter
Eric Cigan is responsible for product management and product marketing in the HDL and SoC design and verification product group. Prior to joining MathWorks in 2007, Eric held product management and business development roles with companies including Mentor Graphics, MathStar, and Analogy in the fields of digital and mixed-signal simulation, high-level synthesis, and hardware/software coverification. Eric earned S.B. and S.M. degrees in mechanical engineering from the Massachusetts Institute of Technology.
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