Generating Space-Compliant HDL Code for a UHF Satellite Communications Processor at Thales Alenia Space
Verified Models Can Be Reused for Future Projects
“We have used Simulink® in other projects and were able to reuse a lot of models from the UHF project. It is easy to create a library of configurable, space-qualified models and reuse them.”
Key Outcomes
- Model-Based Design reduced time to market, enabling delivery of standard-compliant products in about half the time when compared to handwriting code
- Using Model-Based Design reduced and facilitated the number of iterations required between algorithm and FPGA engineers, streamlining the workflow and validation efforts
- Target independence of verified models allowed for reuse on different platforms, eliminating code rewriting and saving time on checking standards
The UHF processor in the casing it will be flown to space in.
The need to accelerate product delivery has rendered handwriting code for radiation-tolerant complex FPGAs for space applications increasingly impractical. In developing a UHF communications processor, Thales Alenia Space—a company with 40 years of expertise in space equipment—adopted Model-Based Design with code generation to overcome this challenge.
The team first aligned Model-Based Design with their internal space standard compliance processes, creating a set of practices for developing space-compliant applications. Algorithm and FPGA engineers together captured modeling standards that reflected model quality and influenced the code generation process and set up checks for these standards using Simulink Check™. These could then be run by the algorithm experts automatically, while the FPGA engineers were able to concentrate on the rest of the system. The generated code is easily readable and always generated in the same way. Beyond this, any part of the code and its corresponding elements in the model can be traced to each other bidirectionally.
The Thales Alenia team then tested the model on a client’s equipment testbench, where the FPGA performed in line with their expectations. The approach facilitated standard compliance verification, as reports from HDL Coder™ and Simulink Check served as evidence. The workflow also reduced the number of iterations between FPGA and algorithm designers.
Using Model-Based Design, Thales Alenia Space reduced development time by 50% when compared to handwriting code. Additionally, with the verified models being target-independent, the team has since reused them for different projects.
