Prototyping and Verifying Wireless Systems on FPGAs and ASICs
From the series: MathWorks Wireless Series: Transforming the Next Generation of Wireless Communication
Designing innovative wireless communication devices requires close collaboration across multiple disciples. New standards like the 3GPP 5G New Radio (NR) standard require deep domain expertise as well as complex hardware architecture, making it even more challenging to realize a real-time system with the necessary performance requirements.
In this talk, you will learn about how MATLAB and Simulink can be used for early ASIC design through pre-verified, hardware-ready reference applications for different wireless communication applications, reuse of algorithm models in production verification environments and FPGA based debugging workflows.
Customer talk – Capgemini
Development of O-RU in UE Emulator for 5G-NR
UE Emulator tests the function and performance of gNodeBs (gNB) to help network operators and equipment vendors create and develop 5G RAN with ORAN Split7.2 architecture. UE Emulator has two major units, O-DU and Intel FPGA based O-RU system. To reduce the compute intensive in O-DU, the NR Cell Search procedure is implemented in O-RU which involves complete SS-Burst processing in FPGA.
In this talk, we will discuss how 5G Toolbox, Wireless HDL Toolbox and HDL coder helped us in developing 3GPP standard compliant models and validation of 5G-NR Cell Search Procedure (with AFC synchronization) along with MIB Recovery on our custom FPGA hardware
- Customer talk by Capgemini
- Creating a reference algorithm and standard-compliant waveform for wireless standards
- Implement streaming version of algorithms and hardware architecture to reference models
- Generating SystemVerilog DPI-C and UVM components from MATLAB algorithms
- Cosimulation of RTL code in simulators like Cadence Incisive and QuestaSim
- Performing top-down design and verification of analog/mixed-signal designs
- Hardware-based verification and prototyping on FPGAs using reference applications
About the Presenters
Niharika Agrawal has received her B.Tech. degree in Electronics and Communication Engineering (ECE) from Poornima Institute of Information Technology, India in 2013 and the MTech degree from LNM Institute of Information Technology, India in 2015. She has submitted her PhD thesis in July. Her main area of research is the waveform design for Air to Ground communication, hardware implementation of end-to-end transceiver architectures using HDL and embedded coder on FPGA. She is currently working as an application engineer in communications and FPGA design at MathWorks.
Vinoth Thuruvas has received the B. E. degree in Electronics and Communications Engineering from Anna University, Chennai in 2005. He has more than 15 years of Industrial experience in the field of Signal processing, Wireless and Optical Communication system design, assuming various roles in SAMEER-CEM, HCL Technologies, Tessolve Semiconductors, and Capgemini.He is currently working as Senior Technical Lead – Capgemini (formerly ALTRAN/Aricent Technologies), Bangalore focusing on complete FPGA based RRH design for 4G-LTE and O-RU 5G-NR systems.
Recorded: 1 Jul 2022
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