Xilinx RFSoC Support from HDL Coder

Generate code for the FPGA portion of RFSoC devices

Xilinx Support from SoC Blockset
Xilinx RFSoC Support from HDL Coder

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Capabilities and Features

HDL Coder Support Package for Xilinx^® Zynq^® UltraScale+™ RFSoC devices enables generation of IP cores that can integrate into RFSoC devices using Xilinx Vivado^® Design Suite.

This support package includes reference designs for popular RFSoC development kits, so you can generate HDL code and port mappings to I/O and AXI registers to interface with RF tiles and DDR memory, and interactively control the FPGA design from MATLAB.

You can use SoC Blockset for system-level modeling of RFSoC devices, configuration of custom RFSoC-based boards, and deployment of complete SoC applications, including executables for ARM^® Cortex-A53 processors.

Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit

Supported Hardware

Device Family	Board
Xilinx Zynq UltraScale+ RFSoC Gen 1	Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit
Xilinx Zynq UltraScale+ RFSoC Gen 3	Xilinx Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit