General Multiplexed Interleaver

Permute input symbols using set of shift registers with specified delays

Library

Convolutional sublibrary of Interleaving

Description

The General Multiplexed Interleaver block permutes the symbols in the input signal. Internally, it uses a set of shift registers, each with its own delay value.

This block accepts a scalar or column vector input signal, which can be real or complex. The input and output signals have the same sample time.

The block can accept the data types int8, uint8, int16, uint16, int32, uint32, boolean, single, double, and fixed-point. The output signal has the same data type as the input signal.

Parameters

Interleaver delay (samples)

A column vector listing the number of symbols that fit into each shift register. The length of this vector is the number of shift registers. (In sample-based mode, it can also be a row vector.)

Initial conditions

The values that fill each shift register at the beginning of the simulation.

If Initial conditions is a scalar, then its value fills all shift registers. If Initial conditions is a column vector, then each entry fills the corresponding shift register. (In sample-based mode, Initial conditions can also be a row vector.) If a given shift register has zero delay, then the value of the corresponding entry in the Initial conditions vector is unimportant.

Pair Block

General Multiplexed Deinterleaver

References

[1] Heegard, Chris and Stephen B. Wicker. Turbo Coding. Boston: Kluwer Academic Publishers, 1999.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

The implementation for the General Multiplexed Interleaver block is shift register based. If you want to suppress generation of reset logic, set the implementation parameter ResetType to'none'.

When you set ResetType to'none', reset is not applied to the shift registers. Mismatches between Simulink^® and the generated code occur for some number of samples during the initial phase, when registers are not fully loaded. To avoid spurious test bench errors, determine the number of samples required to fill the shift registers. Then, set the Ignore output data checking (number of samples) option accordingly. (You can use the IgnoreDataChecking property for this purpose, if you are using the command-line interface.)

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
ResetType	Suppress reset logic generation. The default is `default`, which generates reset logic. See also ResetType (HDL Coder).

Version History

Introduced before R2006a

General Multiplexed Interleaver

Library

Description

Parameters

Pair Block

References

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Objects

Blocks

Topics

General Multiplexed Interleaver

Library

Description

Parameters

Pair Block

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Objects

Blocks

Topics

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.