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Configure FPGA Boards

Prepare your target FPGA boards for deploying a deep learning network by configuring them to connect to your host computer.

Xilinx Zynq-7000 ZC706 Evaluation Board

To set up the board:

  1. Plug in the power cord, and then connect the host computer to the FPGA board by using a JTAG cable.

  2. Specify the SW4 switch settings to use the Digilent USB-TO-JTAG interface.

    Configuration SourceSW4 switch 1SW4 switch 2
    None00
    Cable Connector J310
    Digilent USB-TO-JTAG Interface 01
    JTAG (flying lead) Header J6211

This graphic shows the configuration settings for the Xilinx® Zynq®-7000 ZC706 Evaluation Board.

To learn more about the board configuration, see the Xilinx ZC706 Evaluation Board User Guide.

Intel Arria 10 SoC Development Kit

To set up the board:

  1. Plug in the power cord, and then connect the host computer to the FPGA board by using a JTAG cable.

  2. Specify the SW3 switch settings.

    Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7Bit 8
    OffOnOnOnOnOffOffOff

  3. Connect two DDR4 plugin boards to the memory plugin slot.

This graphic shows the configuration settings for the Intel® Arria® 10 SoC development kit.

To learn more about the board configuration, see the Arria 10 SoC Development Kit User Guide.

Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA Development Board

To set up the board:

  1. Plug in the power cord. If using JTAG, connect the FPGA board to the host computer by using a JTAG cable. If using Ethernet, connect the FPGA board to the host computer by using an Ethernet cable.

  2. Configure the SW6 switch.

    Boot ModeMode Pins [3:0]SW6 Switch Position [3:0]
    JTAG0, 0, 0, 0on, on, on, on
    QSPI320, 0, 1, 0 on, on, off, on
    SD1, 1, 1, 0off, off, off, on

    The SW6 default position is QSPI32. For the SW6 DIP switch, moving the switch towards the ON label is 0.

    This graphic shows the location of the SW6 switch.

This graphic shows the configuration settings for the Xilinx Zynq UltraScale+™ MPSoC ZCU102 FPGA development board.

To learn more about the ZCU102 hardware setup, refer to the Xilinx documentation.