Default System Reference Design for AMD SoC Devices

R2026b

SoC Blockset™ for AMD provides the Default system reference design for the supported Zynq®-7000, MPSoC, and Versal® devices. This reference design supports high-speed data streaming applications. Use this reference design with the IP core generation workflow.

Generate an IP core for a design under test (DUT) and integrate the generated IP core into the Default system reference design. Connect the IP core with rest of the design by using the AXI4-Stream Master, AXI4-Stream Slave, AXI4 Master, interrupt, or AXI4-Lite interfaces. The reference design dynamically adds the required interfaces based on the interface mapping for each DUT port.

The figure shows how the interfaces connect the processor to the DUT.

The reference design includes DMA IPs to handle data streaming between the processor and the IP core. The IP core connects to the external memory using an AXI4 Master interface. The design also includes an interrupt interface from the DUT to the processor.

The reference design includes a processor and the generated IP core. The processor acts as a manager, and the IP core acts as a subordinate. By accessing the generated registers via the AXI4-Lite interface, the processor can read and write data to and from the IP core.

The reference design includes a direct memory access (DMA) IP to handle the data streaming between the processor and the IP core. The DMA controller acts as both a manager and a subordinate. The AXI4-Stream interfaces process the data stream from the DMA controller and send the output data stream back to the DMA controller.

In the IP core, when the TLAST signal in the AXI4-Stream Master interface asserts, the DMA IP identifies the assertion as a package completion signal. The DMA IP then interrupts the processor to indicate that the frame transfer is complete.

The IP core reads the input data from the external memory via the AXI4 Master interface. The IP core then computes the algorithm and writes the result to external memory via the AXI4 Master interface. The processor can read the result from memory and then verify the result in MATLAB®.

You can also insert the AXI manager IP for the JTAG or programmable logic (PL) Ethernet connection into the reference design. Through this IP, you can use the input data in MATLAB to initialize the on-board DDR external memory.

You can tune the parameters on the FPGA or probe the results from the FPGA via the AXI4-Lite interface in the IP core. To tune the parameters or probe results, use this reference design with External mode in Simulink®.

Supported Interface Methods

You can use the Default system reference design with these interfaces:

  • Register Interface (AXI4-Lite or AXI4) — Use this interface to access the control and status registers in your design. You can choose between AXI4-Lite or AXI4 protocol for the register interface. If you need only lightweight data transfers, use AXI4-Lite. Use AXI4 to connect to components that support burst data transfers. For more information, see Register Interface (AXI4-Lite/AXI4) (HDL Coder).

  • AXI4 Master — Use this interface for designs that require you to access memory or to control other IP cores with AXI4 or AXI4-Lite interfaces. Example applications include moving large amounts of data between your algorithm and external DDR memory. For more information, see AXI4 Master (HDL Coder).

  • AXI4-Stream — Use this interface for moving streaming data or transferring data at high speeds. Example applications include transferring large amounts of data between processors and FPGAs using DMA. For more information, see AXI4-Stream (HDL Coder).

  • External I/O and External Port — Use this interface to connect to peripherals on your hardware board, such as LEDs, push buttons, DIP switches, and FPGA pins. For more information, see External I/O and External Port (HDL Coder).

  • FPGA Data Capture — Use this interface to capture raw data from outputs or signals by using test points in your design, and then use the data to debug your design. For more information, see FPGA Data Capture (HDL Coder).

  • Interrupt — Use this interface to send interrupt signal from DUT to processor to trigger an event-driven task.

Supported Boards

You can use the Default system reference design architecture with these target platforms:

  • Xilinx® Zynq ZC702 Evaluation Kit

  • Xilinx Zynq ZC706 Evaluation Kit

  • ZedBoard™

  • Xilinx Zynq UltraScale+™ MPSoC ZCU102 Evaluation Kit

  • Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit

  • Xilinx Versal AI Core Series VCK190 Evaluation Kit

Specifications

These specifications apply when you add the AXI4-Stream interfaces.

  • AXI4-Stream Data signal: Less than or equal to 32 bits

  • DUT interface: Only one AXI4-Stream Slave and one AXI4-Stream Master channel

These specifications apply when you access the external PL DDR memory or shared memory through AXI4 Master interfaces. The specifications vary depending on the target board.

Note

The ZC702 evaluation kit does not include external memory and therefore does not support the AXI4 Master interface.

ZC706 Evaluation Kit

If you specify Xilinx Zynq ZC706 evaluation kit as the target platform, the reference design specifications include:

  • Support for either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels

  • AXI4 Master Maximum Data bitwidth: 1024-bit

  • AXI4 Master Address bitwidth: 32-bit

For DUT IP core AXI4 Master interface:

  • DDR3 external memory address range: x80000000 to xBFFFFFFF

  • Default AXI4 Master Read channel base address: x80000000

  • Default AXI4 Master Write channel base address: x81000000

For MATLAB AXI Manager interface:

  • DDR3 external memory address range: x80000000 to xBFFFFFFF

  • DUT IP core base address: x400D0000

ZedBoard

If you specify ZedBoard as the target platform, the reference design specifications include:

  • Support for either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels

  • AXI4 Master Maximum Data bitwidth: 1024-bit

  • AXI4 Master Address bitwidth: 32-bit

For DUT IP core AXI4 Master interface:

  • Shared memory address range: 0x10000000 to 0x18000000

  • Default AXI4 Master Read channel base address: 10000000

  • Default AXI4 Master Write channel base address: 12000000

ZCU102 or ZCU106 Evaluation Kit

If you specify Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit or Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit as the target platform, the reference design specifications include:

  • Support for either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels

  • AXI4 Master Maximum Data bitwidth: 1024-bit

  • AXI4 Master Address bitwidth: 32-bit

For DUT IP core AXI4 Master interface:

  • DDR4 external memory address range: x80000000 to x9FFFFFFF

  • Default AXI4 Master Read channel base address: x80000000

  • Default AXI4 Master Write channel base address: x90000000

For MATLAB AXI Manager interface:

  • DDR4 external memory address range: x80000000 to x9FFFFFFF

  • DUT IP core base address: xA0000000

VCK190 Evaluation Kit

If you specify Xilinx Versal AI Core Series VCK190 Evaluation Kit as the target platform, the reference design specifications include:

  • Support for either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels

  • AXI4 Master Maximum Data bitwidth: 1024-bit

  • AXI4 Master Address bitwidth: 64-bit

For DUT IP core AXI4 Master interface:

  • LPDDR4 external memory address range: 0x50000000000 to 0x501FFFFFFFF

  • Default AXI4 Master Read channel base address: 50000000000

  • Default AXI4 Master Write channel base address: 50000000000

For MATLAB AXI Manager interface:

  • LPDDR4 external memory address range: 0x50000000000 to 0x501FFFFFFFF

  • DUT IP core base address: xA4000000

Target Algorithm to Reference Design

To target your algorithm in Simulink to the Default system reference design:

  1. Model your algorithm.

  2. On the Simulink Toolstrip, on the HDL Code tab, in the Output section, set the drop-down button to IP Core.

  3. Select your DUT and make sure that Code for is set to this DUT.

  4. To open the Configuration Parameters dialog box, click the Settings button. Then, select HDL Code Generation > Target.

  5. Set Target Platform to a supported hardware board listed in Supported Boards. Check that the Synthesis Tool is set to Xilinx Vivado.

  6. Set Reference Design to Default system.

    Configuration Parameters dialog box open on the HDL Code Generation > Target tab, with the Reference Design parameter highlighted in the right pane.

Alternatively, you can set the target reference design by using the HDL Workflow Advisor tool:

  1. In the 1.1. Set Target Device and Synthesis Tool step, set Target workflow to IP Core Generation. Set Target platform to a supported hardware board listed in Supported Boards. Check that Synthesis tool is set to Xilinx Vivado.

  2. In the 1.2. Set Target Reference Design step, set Reference design to Default system.

    HDL Workflow Advisor open on the 1.2. Set Target Reference Design step, with the Reference design parameter highlighted in the right pane.

    Go through the workflow to generate the HDL IP core, and then integrate the IP core into the selected reference design.

Set Reference Design Parameters

In the Configuration Parameters dialog box, on the HDL Code Generation > Target pane, set reference design parameters to the required values. The Default System with SoC Blockset reference design has these configuration parameters:

  • AXI4-Stream Master data width — Specify data width for AXI4-Stream Master interface as 32, 64, or 128 bits.

  • AXI4-Stream Slave data width — Specify data width for AXI4-Stream Slave interface as 32, 64, or 128 bits.

  • FPGA Data Capture — Generate and integrate the data capture IP into the reference design. Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB or Simulink over a JTAG connection. To capture data over a JTAG connection, set this parameter to JTAG. To capture data over an Ethernet connection, set this parameter to PL Ethernet. Then, map each signal that you want to capture to the FPGA Data Capture interface.

    Note

    • FPGA data capture in Configuration Parameters or HDL Workflow Advisor support programmable logic (PL) Ethernet only. The processing system (PS) Ethernet is not supported.

    • To enable the PL Ethernet option for the Xilinx boards that have the Ethernet physical layer (PHY), manually add the Ethernet media access controller (MAC) Hub IP in the plugin_board file using the addEthernetMACInterface (HDL Coder) method before you open the Configuration Parameters dialog box or HDL Workflow Advisor.

    • FPGA data capture in Configuration Parameters or HDL Workflow Advisor does not support SGMII interface.

Map DUT Ports

To automatically map the DUT ports to the required interfaces, on the System on Chip tab, click Map Interfaces.

To view and edit the interface mapping:

  1. On the HDL Code tab, click Target Interface to open the IP Core editor.

  2. Select the Interface Mapping tab to map each DUT port to one of the IP core target interfaces. If no mapping table appears, click the Reload IP core settings Icon to update the interface mapping table button to compile the model and repopulate the DUT ports and their data types.

  3. Validate your settings by clicking the Validate IP core settings Icon to validate IP core configuration settings button.

Generate IP Core and Program FPGA

Generate the IP core and the FPGA bitstream file. Then, program the FPGA:

  1. In the Simulink Toolstrip, on the HDL Code tab, click Build Bitstream to generate the IP core and bitstream file. Wait until the synthesis tool runs in the external window.

  2. Expand the Build Bitstream menu. To download the bitstream, select Program Target Device.

Generate Host Interface Script

Verify the generated IP core on the hardware board by using the generated host interface script. This script contains the DUT ports and interface mapping information. Use this script to access the board memory, DUT registers, and AXI4-Stream interfaces from MATLAB. To generate a host interface script file, in the Simulink Toolstrip, on the HDL Code tab, expand the Host Interface Script menu. Then, select Host Interface Script. This option generates these MATLAB files:

  • gs_modelName_setup — This script adds the AXI4 Slave, AXI4-Stream, and memory interfaces. The script also contains DUT port objects that contain the port name, direction, data type, and interface mapping information. The script then maps the DUT ports to the corresponding interfaces.

  • gs_modelName_interface — This script creates a target object, instantiates the setup script gs_modelName_setup, and then connects to the target hardware. The script then sends read and write commands to the generated HDL IP core.

For more information about host interface script, see Host Interface Script Files (HDL Coder).

Generate Software Interface Model

To target your hardware board, you can generate a software model in addition to the FPGA model. This action generates two models: a hardware interface model and a software interface model. It also generates two libraries that contain the interface blocks used in the generated models.

The software interface model and its library are generated only if you have Embedded Coder®, SoC Blockset for AMD, and SoC Blockset Support Package for AMD FPGA and SoC Devices installed.

  • You can use the hardware interface model to control the reference design on the board, including IP core, from the Simulink model, without Embedded Coder.

  • The software interface model enables you to target your software algorithms to the ARM® processor on the board.

For more information about software interface model, see Generate SoC Software Model.

See Also

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