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HDL Construct Properties

Customize HDL constructs in generated code

With the HDL construct properties, you can customize VHDL and Verilog constructs in the generated code.

Specify these properties as comma-separated pairs of Name,Value arguments to the generatehdl function. Name is the property name and Value is the corresponding value. Name must appear inside single quotes (' '). You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

For example:

fir = dsp.FIRFilter('Structure','Direct form antisymmetric');
generatehdl(fir,'InputDataType',numerictype(1,16,15),'CastBeforeSum','off');

HDL Coding Style

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Type casting before addition or subtraction, specified as one of the following:

  • 'on' — The generated code type-casts input values of addition and subtraction operations to the desired result type before operating on the values. This setting produces numeric results that are typical of DSP processors.

  • 'off' — The generated code preserves the input value types during addition and subtraction operations and then converts the result to the desired type.

By default, the coder sets CastBeforeSum based on the Cast signals before sum Filter Designer setting of the filter object. Use this property to override the inherited setting, see Relationship With Cast Before Sum in Filter Designer. For System objects, the default setting depends on the filter type and structure.

Generate inline VHDL configurations, specified as one of the following:

  • 'on' — The coder includes configurations for the filter entity within the generated VHDL code.

  • 'off' — The coder omits the generation of configurations. Use this option if you are creating your own VHDL configuration files.

Loop unrolling in generated VHDL code, specified as one of the following:

  • 'off' — The coder includes FOR and GENERATE loops in the generated VHDL code.

  • 'on' — The coder unrolls and omits FOR and GENERATE loops in the generated VHDL code. Use this option if your EDA tool does not support GENERATE loops.

Type-safe syntax for concatenated zeros, specified as one of the following:

  • 'on' — The coder uses the '0' & '0' syntax for concatenated zeros. This syntax is recommended because it is unambiguous.

  • 'off' — The coder uses the "000000..." syntax for concatenated zeros. This syntax can be easier to read and is more compact, but it can lead to ambiguous types.

Represent constant values by aggregates, specified as one of the following:

  • 'off' — The coder represents constants less than 32 bits as scalars, and constants greater than or equal to 32 bits as aggregates. The following example shows the default scalar declaration for constants of less than 32 bits.

    CONSTANT coeff1: signed(15 DOWNTO 0) := to_signed(-60, 16); -- sfix16_En16
    CONSTANT coeff2: signed(15 DOWNTO 0) := to_signed(-178, 16); -- sfix16_En16
    

  • 'on' — The coder represents constants by aggregates, including constants that are less than 32 bits wide. The following example shows constants of less than 32 bits declared as aggregates.

    CONSTANT c1: signed(15 DOWNTO 0):= (5 DOWNTO 3 =>'0',1 DOWNTO 0 => '0',OTHERS =>'1');
    CONSTANT c2: signed(15 DOWNTO 0):= (7 => '0',5 DOWNTO 4 =>'0',0 => '0',OTHERS =>'1');
    

VHDL coding style to check for rising edges when operating on registers, specified as one of the following:

  • 'off' — The generated code checks for clock events when operating on registers. For example:

    Delay_Pipeline_Process : PROCESS (clk, reset)
    BEGIN
      IF reset = '1' THEN
        delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
      ELSIF clk'event AND clk = '1' THEN
        IF clk_enable = '1' THEN
          delay_pipeline(0) <= signed(filter_in);
          delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
        END IF;
      END IF;
    END PROCESS Delay_Pipeline_Process ;
    
  • 'on' — The generated code uses the VHDL rising_edge function to check for rising edges when operating on registers. For example:

    Delay_Pipeline_Process : PROCESS (clk, reset)
    BEGIN
      IF reset = '1' THEN
        delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
      ELSIF rising_edge(clk) THEN
        IF clk_enable = '1' THEN
          delay_pipeline(0) <= signed(filter_in);		
          delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
        END IF;
      END IF;
    END PROCESS Delay_Pipeline_Process ;
    

When the clock transitions from 'X' to '1', the two coding styles have different simulation behavior.

Use Verilog ˋtimescale compiler directive, specified as 'on' or 'off'. The ˋtimescale directive provides a way of specifying different delay values for multiple modules in a Verilog file. When this property is set to 'off', the coder excludes the directive in the generated Verilog code.

Tips

If you use the fdhdltool function to generate HDL code, you can set the corresponding properties on the Global Settings > Advanced tab in the Generate HDL dialog box.