Minimum Variance Distortionless Response Beamformer Using AMD RFSoC Device

This example uses:

This example shows how to deploy a minimum variance distortionless response (MVDR) algorithm on an AMD® RFSoC evaluation kit using SoC Blockset™. On top of the Conventional and Adaptive Beamformers example, this example adds the infrastructure and connectivity around the device under test (DUT) to implement the design on hardware. Use MATLAB® to:

Program the hardware
Generate test data for transmission on hardware
Control the deployed design
Apply the MVDR beamforming on the received samples
Verify the received data by demodulating and displaying the constellation and the MVDR response

Supported Hardware Platforms

AMD Zynq® UltraScale+™ RFSoC ZCU111 Evaluation Kit + XM500 balun card

AMD Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit + XM655 balun card

AMD Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit + XM655 balun card

File Structure

This example uses these files.

Simulink Models

soc_mvdr_beamformer_zcu111_top.slx, soc_mvdr_beamformer_zcu216_top.slx, and soc_mvdr_beamformer_zcu208_top.slx: Top-level SoC implementation of the example for the ZCU111, ZCU216, and ZCU208 evaluation kits, respectively. The model integrates the FPGA model, soc_mvdr_beamformer_fpga.slx, to the RF data converter and AXI-Stream and AXI-Lite interfaces.
soc_mvdr_beamformer_fpga.slx: Model to implement the test signal generation, signal reception, MVDR algorithm, signal capture, and interface logic.

MATLAB Code and Scripts

soc_mvdr_beamformer_init.m: MATLAB script to generate QPSK test and interferer waveforms and initialize parameters for soc_mvdr_beamformer_zcu111_top.slx.
soc_mvdr_beamformer_setup.m: MATLAB script to program the hardware with the generated configuration files.
SoCRFSoCMVDRDemo.m: Helper class containing methods to configure, control, and run the example.
soc_mvdr_beamformer_host_run.m: Main MATLAB script to run the example.

Helper Files

generate_qpsk_signal.m: MATLAB helper function to generate the QPSK test and the interferer signal.
plot_beam_patterns.m: MATLAB helper function for plotting MVDR and phase shift beam pattern.
qpsk_receive.m: MATLAB helper function for QPSK symbol alignment and decoding.
updatePlot.m: MATLAB helper function for plotting MVDR and phase shift beam pattern.
interleave_complex.m deinterleave_complex.m: MATLAB helper function to interleave and deinterleave real and imaginary components from the input vector.
maxabs.m: MATLAB helper function to get the maximum absolute value of the input data.

Design Task

Beamforming is an important part of many systems such as phased array radar and cellular networks, offering advantages including higher data rates, improved coverage, reduced power consumption, and enhanced overall system capacity. In this example, you design an MVDR-based receiver system to receive and recover a signal transmitted by a source in a specific direction in the presence of an interfering source in the channel. The design task is to model the complete MVDR beamformer system in an SoC Blockset model and implement the system on an RFSoC device. The system consists of a test signal transmitter, which includes the signal of interest and the interfering signal in the transmit path, receive signal capture, an MVDR beamformer, and DMA to the processor memory.

The transmitter generates the QPSK signal of interest and the QPSK interfering signal from the samples stored in the FPGA RAM. The steering channels are generated for the two signals based on the steering coefficients for the signals of interest and interfering signal. A synthesized signal consisting of the signal of interest and the interfering signal is generated for all four channels, which are then fed to the respective DAC channels on the RFSoC device. You can configure the transmitter parameters during the design phase or before deployment.

The receiver receives a combined version of all the transmitted signals, namely the signal of interest and the interfering signal. This signal of interest is extracted using the MVDR beamformer algorithm based on configured receive steering coefficients. The MVDR beamformer preserves the gain in the direction of arrival of the desired signal and attenuates interference from other directions. The receiver system then captures the signal and transfers the samples to host MATLAB over FPGA I/O. You can then visualize and analyze the signals.

The design also integrates a calibration mechanism to calibrate the impairments in the system. For this, a tone is generated from an NCO and transmitted through all the DAC channels of the RFSoC device. The received tone on each of the ADC channels is captured, and calibration coefficients are identified for each of the channels. The identified calibration coefficients are then applied in runtime on each of the receive channels for optimum performance during normal operation.

System Specifications

The system has these high-level specifications:

Beamformer Parameters

Number of array elements: 4
Moving average window size: 4096
Diagonal loading value: 5e-3

RF Data Converter Parameters

Sample rate:1966.08e6
DDC/DUC decimation and interpolation factor: 8
FPGA clock rate: 245.76
Samples per clock cycle: 1
Number of ADC and DAC channels: 4
Sample data width: 16*2 bits
Multi tile sync (MTS): Enabled

Test Signal Parameters

Number of frames: 15
Frame length: 256
Preamble length: 13
Samples per symbol: 4

Interfering Signal Parameters

Number of frames: 7
Frame length: 128
Preamble length: 13
Samples per symbol: 16

Control Configuration and Monitoring Parameters

Internal loopback mode: true/false
Signal gain: -6dB
Signal angle: 40
Interfering signal gain: 0dB
Interfering signal angle: -40
Receiver steering angle: 40

DMA Capture Parameters

For QPSK demodulation, this example captures three frames of data to ensure it contains at least one full contiguous frame. The S2MM DMA frame size and buffers are 3072 and 4, respectively.

This figure shows the block diagram of the MVDR system.

Design MVDR Beamformer

Create the soc_mvdr_beamformer_zcu111_top SoC model as the top model and set the hardware board to the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit. This model includes the soc_mvdr_beamformer_fpga FPGA model as a model reference. The top model also includes an AXI4-Stream to Software block, which shares the external memory between the FPGA and the processor. Additionally, the top model includes the register interface channel for configuration and control. It also includes a software interface behavioral testbench block for simulating the software behavior.

open_system('soc_mvdr_beamformer_zcu111_top')

close_system('soc_mvdr_beamformer_zcu111_top')

Configure RF Data Converter

RFSoC devices have an RF Data Converter hardware IP connected to the programmable logic, which you configure according to your needs. Use the RF Data Converter block to configure the ADC and DAC settings of the Xilinx RF Data Converter IP and emulate the programmable logic interface to the converters.

To meet the system requirements, configure the RF Data Converter block by following these steps.

1. Choose the decimation factor and ADC sample rate based on the specification.

Set DAC and ADC sample rate to 1966.08e6. This value is the lowest sampling rate satisfying the Nyquist criterion that you can derive from the RF PLL reference on the ZCU111 board.

To achieve sample rate of 245.76 MHz, set the Decimation mode to 8 and Interpolation mode to 8.

2. Set Samples per clock cycle to 1 so that the FPGA clock rate is 245.76 MHz. The FPGA clock rate is the sampling rate divided by the product of the decimation factor and the number of samples per clock cycle, which in this case is equal to (1966.08/8) MHz or 245.76 MHz.

3. To select specific ADCs and DACs, set RF interface to Customize. To use the real interface, set the Digital interface to Real.

4. In DAC Tile 0, select DAC 0, DAC 1, DAC 2, and DAC 3. In ADC Tile 2 and ADC Tile 3 select ADC 0 and ADC 1.

5. Select Multi tile sync from the Common Parameters section in the Advanced tab of the RF Data Converter block mask to enable multi-tile synchronization.

The ZCU111 evaluation kit comes with an XM500 eight-channel SMA breakout card. This card has four ADC and four DAC differential channels.

Hardware Logic Design

The soc_mvdr_beamformer_fpga FPGA model contains the MVDR Tx-Rx System, which includes two subsystems: Tx Signal generation and Receiver processing.

open_system('soc_mvdr_beamformer_fpga')

close_system('soc_mvdr_beamformer_fpga')

The Tx Signal generation subsystem consists of the Tx Source LUT, Generate Steering Channels, and Calibration NCO subsystems. The Tx Source LUT generates the test signal and the interfering signal. The Generate Steering Channels subsystem generates the steered signal data based on the steering coefficients. The Sum Channels subsystem finally generates samples for each of the DAC channels.

The Receive processing subsystem implements the core receiver signal processing. The Rx Input Preparation subsystem applies the calibration coefficients to the input to normalize the signal. The Rx Beamforming subsystem performs the MVDR beamforming on the input data. Finally, the Rx Beamforming subsystem output is captured by the Rx Data Capture subsystem for transfer to the host, where subsequent processing takes place.

Host Logic Design

The soc_mvdr_beamformer_host_run MATLAB script initializes the MVDR system running on the FPGA from the host. During the initialization, system calibration is first performed. When calibration is complete, the system is ready to receive the actual test signal.

The beamformed signal is captured using the FPGA I/O functions, and QPSK demodulation is performed on these samples. The demodulated QPSK samples are then plotted to show the signal recovery. Additionally, the computed weights of the MVDR algorithm are also captured on the host to display them. The SoCRFSoCMVDRDemo class implements the SoC Blockset MVDR system and has methods to configure, control, and acquire the calibration and received samples from the system running on the RFSoC device.

Simulate MVDR System

Open and simulate the model. Run the model to visualize the output. You can adjust the signal direction, steering angle, and interference angles by editing the constant values during initialization.

The simulation outputs two plots containing the MVDR beamformer response and the QPSK constellation of the received beamformed signal.

When the signal direction and signal steering angle are aligned, and the interfering angle is different, as indicated by the red and green lines, you can see that the beam pattern has a gain of 0 dB. The noise sources are nulled, as indicated by the red lines.

The QPSK constellation of the signal of interest appears clean when the noise sources are nulled. This example simulates with the same latency as the hardware, so you can see the signal settle over time as the simulation starts.

Implement and Run Model on Hardware

Configure Hardware

Connect the SMA connectors on the XM500 balun card to complete the loopback between the DAC and ADC channels, according to the connections mentioned in the table below. Since all the selected channels are differential, a DC block is required between the DAC and the ADC P and N connections to block the DC. You require eight loopback cables and eight DC blocks for the four differential channels.

You can use the internal loopback mode to verify the design in case you do not have the above accessories available, such as the loopback cables and DC block.

To implement the model on a supported SoC board, select the appropriate top model and use the SoC Builder (SoC Blockset) tool.

To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.

On the Setup screen, select Build model, click Next.
On the Select Build Action screen, select Build load and run, click *Next.
On the Select Project Folder screen, specify the project folder, click Next.
On the Review Hardware Mapping screen, click Next.
On the Review Memory Map screen, to view the memory map, click View/Edit. Click Next.
On the Validate Model screen, to check the compatibility of the model for implementation, click Validate. Click Next.
On the Build Model screen, to build the model, click Build. An external shell opens when FPGA synthesis begins. Click Next.
On the Connect Hardware screen, to test the connectivity of the host computer with the SoC board, click Test Connection. To go to the Run Application screen, click Next.

The FPGA synthesis often takes more than 30 minutes to complete.

Validate FPGA Design

Click Load and Run to load the pre-generated bitstream. You can use the automatically generated FPGA I/O script during the build process to quickly verify the FPGA algorithm. To validate the FPGA algorithm, load the bitstream and follow these steps.

Open the soc_mvdr_beamformer_host_run ') soc_mvdr_beamformer_host_run script.
Set the IP address of the ZCU111 board in the IPAddress field.
Run the script by clicking the Run button.

The script generates two plots similar to the simulation, containing the MVDR beamformer response and the QPSK constellation of the received and beamformed signal. The default value of the signal angle is 40 degrees, where the signal is maximum. The angle of the interfering signal is -40 degrees, where the MVDR is adaptively reducing the gain. You can try modifying the parameters in the configuration, such as the interfering angle and signal angle, with different values from the MATLAB script. You can then check the plots if the MVDR algorithm responds to the inputs accordingly.

Try Different Hardware Boards

The example is also supported on the ZCU216 and ZCU208 evaluation kits. To run the example on these kits, use the soc_mvdr_beamformer_zcu216_top and soc_mvdr_beamformer_zcu208_top models, respectively. The four ADC and DAC channels required for each of the evaluation kits are configured in the respective top models. soc_mvdr_beamformer_fpga is a referenced model and is common to all the top models. Repeat the steps from the above 'Implement and Run on Hardware' section to run on the ZCU216 or ZCU208 hardware board.

Hardware Setup for ZCU216 and ZCU208

Connect the XM655 balun card and complete the loopback between the DACs and ADCs as shown in the table below. You can use the two Carlisle Core HC2 cables that come with the evaluation kit to loop back the four DAC and ADC channels required for this example.

Conclusion and Further Exploration

This example shows how to simulate and deploy the MVDR algorithm on an RFSoC evaluation kit using SoC Blockset. The example uses a pre-generated QPSK waveform as the test signal. You can replace it with your waveform of interest.