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AND

Bitwise AND

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  • AND block

Libraries:

Description

The AND block implements the AND ladder logic instruction. When the rung conditions are true, the block performs bitwise AND operation on the values at source A with the values at source B. The result of this operation is available at the destination port (dest).

Ports

Input

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Controls the execution of the block. EnableIn reflects the rung state preceding the block. If the rung state preceding the block is false, EnableIn is false, the block does not execute and the outputs are not updated.

The first input signal to the bitwise AND operation. If the datatype is single (REAL – ladder logic equivalent), the input value is converted to int32 (DINT – ladder logic equivalent). int8, int16 (SINT,INT – ladder logic equivalent) datatypes are converted to int32 (DINT – ladder logic equivalent) by filling the upper bits with 0s.

Data Types: int8 | int16 | int32 | single

The second input signal to the bitwise AND operation. If the datatype is single (REAL – ladder logic equivalent), the input value is converted to int32 (DINT – ladder logic equivalent). int8, int16 (SINT,INT – ladder logic equivalent) datatypes are converted to int32 (DINT – ladder logic equivalent) by filling the upper bits with 0s.

Data Types: int8 | int16 | int32 | single

Output

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By default, EnableOut follows the state of EnableIn. If the EnableIn input to the block is false, the logic implemented by the block is not executed and EnableOut signal is set to false.

Output signal resulting from the bitwise AND operation. If the datatype is single (REAL – ladder logic equivalent), the resultant int32 (DINT – ladder logic equivalent) is converted to REAL (single – ladder logic equivalent).

Data Types: int8 | int16 | int32 | single

Version History

Introduced in R2019a

See Also

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