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Leverage target hardware instruction set extensions

Instruction sets to generate single instruction, multiple data (SIMD) code

Since R2021b

Model Configuration Pane: Code Generation / Optimization

Description

The Leverage target hardware instruction set extensions parameter specifies the instruction sets to use to generate single instruction, multiple data (SIMD) code for target hardware.

Dependencies

To use this parameter, you must set Device vendor and Device type to a combination of values from this table. You can also use this parameter if you set Hardware board to a board that results in the device settings from this table.

Device vendorDevice type
Intelx86-64 (Windows 64)
x86-64 (Linux 64)
AppleARM 64
AMDAthlon 64
ARM CompatibleARM Cortex-A (32-bit)
ARM Cortex-A (64-bit)
GenericMATLAB Host Computer

Intel, AMD, ARM Compatible, or Generic and Device type to x86-64 (Windows 64), x86-64 (Linux 64), Athlon 64, ARM Cortex-A (32-bit), ARM Cortex-A (64-bit), or MATLAB Host Computer. If you use MATLAB Host Computer, you can choose only instruction sets that are supported by your computer.

Settings

SSE2 | SSE | SSE4.1 | AVX | AVX2 | FMA | AVX512F | Neon v7 | None

Instruction sets for GRT-based targets for Intel® hardware:

  • SSE2 (default)

  • None — Does not generate SIMD code.

Instruction sets for ERT-based targets for Intel hardware:

  • SSE (default)

  • SSE2

  • SSE4.1

  • AVX

  • AVX2

  • FMA

  • AVX512F

  • None — Does not generate SIMD code.

Instruction sets for ERT-based targets for Apple silicon and ARM® Cortex®-A hardware:

  • None (default) — Does not generate SIMD code.

  • Neon v7

The list of instruction sets for ERT-based targets shows the dependency of the instruction sets, where each instruction set depends on the instruction sets that precede it. The code generator loads the selected instruction set and the instruction sets that it depends on. For example, if you select AVX, the code generator loads AVX, SSE4.1, SSE2, and SSE. If you select SSE2 for a GRT-based target or an ERT-based target, the code generator loads SSE2 and SSE.

Recommended Settings

ApplicationSetting
DebuggingNo impact
TraceabilityNo impact
EfficiencyNo impact
Safety precautionNo impact

Programmatic Use

Parameter: InstructionSetExtensions
Type: character vector
Value: 'None' | 'SSE' | 'SSE2' | 'SSE4.1' | 'AVX' | 'AVX2' | 'FMA' | 'AVX512F'| 'Neon v7'

Limitations

  • For some custom toolchains, you must set Instruction set extensions to None. This limitation occurs if your custom toolchain does not generate the compiler flags required by the SIMD instruction sets, leading to code that does not compile.

    A custom toolchain may support SIMD instruction sets if it was derived from a built-in toolchain or if it inserts the compiler flags required by the instruction sets by default.

  • For some blocks in DSP System Toolbox™, to generate SIMD code, you must set Optimization levels > Priority to Balance RAM and speed or Maximize execution speed.

Version History

Introduced in R2021b

See Also

Topics