This example shows how to create IEEE 802.3ck specification ADC-based transmitter and receiver IBIS-AMI models using library blocks in the SerDes Toolbox™ library and custom blocks to model a time-agnostic ADC. The generated models conform to the IBIS-AMI standard. The virtual sampling node, which exists in slicer-based SerDes systems, but does not exist in ADC-based SerDes systems, is emulated to allow for virtual eye diagram generation in the Simulink® and IBIS-AMI simulators for evaluating the channel.
This example uses a MATLAB® script to first construct a SerDes System representing the transmitter and receiver of an ADC architecture and then export to a SerDes Simulink model. Type this command in the MATLAB command window to run the script:
A SerDes System is configured with the following attributes before being exported to Simulink. Note that custom blocks will function as pass-throughs until the Simulink customizations discussed later in the example are applied.
Symbol Time is set to 18.8235ps, since the maximum allowable 802.3ck operating data-rate is 106.25Gb/s.
Target BER is set to 1e-4.
Samples per Symbol is set to 32.
Modulation is set to PAM4.
Signaling is set to Differential.
The Tx FFE block is set up for 3 pre-tap and 1 post-tap by including 5 tap weights.
The Tx VGA block is used to control the launch amplitude.
The Tx AnalogOut model is set up so that Voltage is 1V, Rise time is 6.161ps, R (output resistance) is 50 Ohms, and C (capacitance) is 5fF according to the 802.3ck specification.
Channel loss is set to 15dB.
Target Frequency is set to the Nyquist frequency.
Differential impedance is kept at default 100 Ohms.
The Rx AnalogIn model is set up so that R (input resistance) is 50 Ohms and C (capacitance) is 5 fF according to the 802.3ck specification.
The Noise custom block injects Gaussian noise to time domain waveform.
A cascade of 3 Rx CTLE blocks is set up for 7, 21, and 1 configurations respectively. The GPZ (Gain Pole Zero) matrix data for each is derived from the transfer function given in the 802.3ck behavioral CTLE specification.
The Rx VGA custom block applies adapted gain.
The Saturating Amplifier block applies memoryless non-linearity.
The ADC custom block quantizes the time domain signal.
The Rx FFE custom has 21 taps (3-pre and 17-postcursor taps) whose weights will be automatically computed during the Rx global adaptation.
The Rx DFECDR block is set up for one DFE taps. The DFE tap is limited to be +/- 0.5V amplitude.
The second part of this example takes the SerDes system exported by the script and customizes it as required for an ADC-based SerDes in Simulink.
The SerDes System exported into Simulink consists of Configuration, Stimulus, Tx, Analog Channel and Rx blocks.
Push inside the Tx subsystem.
Push inside the Rx subsystem.
The model exported from the SerDes App needs to be first customized to represent an ADC-based SerDes Rx by customizing additional Rx blocks and modifying the Rx Init block code.
Noise in the Rx subsystem can be modelled at the output, or at the input. An input referred noise source is shaped by the subsequent equalization stages (CTLE & FFE), and hence better reflects the how noise is shaped by the real system. On the other hand, output referred noise is not shaped, and does not capture how changing the settings on the CTLE and FFE impact noise.
Descend into the Pass-Through block named Noise by clicking on the down arrow on block.
Point the existing system object to the Noise.m system object in the example directory. See Implement Custom CTLE in SerDes Toolbox PassThrough Block.
In the system object mask, configure Symbol Time, Sample Interval, and Modulation with the system variables.
Create an IBIS-AMI parameter in the IBIS-AMI Manager for the Noise block named NoisePSD using the pictured attributes. The value 8.2e-9 comes from the COM standard. See Managing AMI Parameters.
Connect the generated constant block to Noise input port.
Descend into the Pass-Through block named VGA.
Point the existing system object to the serdes.VGA system object included in SerDes Toolbox.
In the system object mask, turn off the Mode Port to force the block to be on.
Create an IBIS-AMI parameter in the IBIS-AMI Manager for the VGA block named Gain using the pictured attributes.
Connect generated data store read to Gain input port. Delete data store write as it will be unused because the value is only updated in Init and not time domain.
VGA adaptation is straightforward, the required gain is calculated in Init as the ratio of a target pulse amplitude versus the maximum peak value of the input pulse response. Yet, the required VGA gain may be different for different CTLE settings, hence the VGA gain will need to be evaluated at each iteration of the general algorithm described previously.
The ADC model used is a time-agnostic ADC, meaning that each point in the simulation is quantized, rather than just at the sampling instant. However, the DFE and clock recovery will still only use ADC samples at the sampling instant. A time-agnostic ADC allows for the generation of an equivalent waveform as seen at the DFE summing node: allowing for the construction of a signal eye diagram with a representative height and width.
Descend into the Pass-Through block named ADC
Point the existing system object to the ADC.m system object in the example directory.
In the system object mask, configure Symbol Time, Sample Interval, and Modulation with the system variables.
Descend into the Pass-Through block named Rx_FFE
Point the existing system object to the serdes.FFE system object included in SerDes Toolbox.
In the main tab of the system object mask, turn off the Mode Port and turn off Normalize Taps. In the advanced tab, configure Symbol Time and Sample Interval with the system variables.
Create a tap structure in the IBIS-AMI Manager for the Rx_FFE block with 3 pre-cursor taps, 17 post cursor taps, and the pictured attributes.
[zeros(1,3) 1 zeros(1,17)]
Connect generated data store read to Tap Weights input port. Delete data store write as it will be unused.
The Rx FFE operates on ADC sampled data, rather than on a continuous waveform. However, during statistical adaptation, it is assumed that all of the waveform points, even in between data samples, are available. The Rx FFE is only adapted in the custom user Init code; adaptation is assisted by the adaptFFE function provided. The Rx FFE adaptation goal is to drive the output pulse response, given an input pulse response, such that the pre and post cursor data samples are driven to zero. This does not mean that the pulse response will be zero other than at the cursor point. Rather, much like a sync waveform, the ISI is only driven to zero at the data sample points.
As the Rx FFE operates on sampled data, the first step in the adaptation process, in adaptFFE, is to assume a data sampling phase for the input pulse response. The approach used is greedy to assume that we can force sampling so that the cursor lands on the peak of the incoming pulse response.
As the Rx FFE, in the Rx subsystem, is followed by a 1-tap DFE, the Rx FFE does not need to zero force the 1st post cursor. Rather, the Rx FFE needs to ensure that the 1st post-cursor falls within the equalization range of the 1-tap DFE. Note, that if a post Rx DFE is not used, then the goal would be to zero-force all pre- and post-cursor ISI.
Given the now sampled input pulse response, the goal is to find a filter response that drives the pre- and post-cursor data samples to zero, or in the case of the 1st post cursor sample into the range of the DFE. This optimization problem is very closely related to solving a set of linear equations, where we need to find a matrix inverse. This matrix that needs to be inverted is a matrix made up of the circularly shifted input sampled pulse response. This inverted matrix then multiplied by the desired output target pulse response: [0, 0, 0, 1, bmax, 0, 0…] for the case of a 3-tap precursor Rx FFE, where the 1 denotes the cursor position and bmax denotes the maximum range of the DFE. The required Rx FFE FIR filter coefficients are the product of the inverted, circularly shifted input pulse-response matrix and the desired output pulse response.
DFECDR adaptation follows Rx FFE adaptation. The DFECDR is the standard block in the SerDes toolbox, please refer to the online documentation for the DFECDR block.
This example uses an Alexander (bang-bang) phase detector, rather than a baud-rate phase detector that is typically used in ADC-based SerDes systems. This modelling choice simplifies the example, as a baud-rate phase detector would interact with the adaptation convergence. The ADC-based SerDes systems need to contend with the interaction between CDR lock point and Rx FFE & DFE adaptation.
In this example, the Rx subsystem adaptation is performed in the statistical domain: involving the co-adaptation of the CTLE, FFE, and DFE to achieve the best possible BER given the channel and Tx FFE settings used. The optimized settings for CTLE and FFE will remain fixed during time-domain simulations, while the DFE and CDR continue to adapt during the time-domain simulation.
Modify the custom user code area of Init with the code provided with the example. See Globally Adapt Receiver Components Using Pulse Response Metrics to Improve SerDes Performance.
Click Refresh Init on the Init mask dialog to update code based on previous steps.
Click Show Init on the Init mask dialog to open the Init code.
Copy the code in
adcInitCustomUserCode.m within the example directory.
Paste the copied code just before the end of the custom user code area. Ensure that the AMI parameters at the top of the custom user area are retained. Do not modify code beyond the end of the custom user area.
The statistical adaptation algorithm processes the impulse response though each of the Rx subsystem blocks, and measures the resulting impulse response figure of merit. As this is an ADC-based system, the figure of merit used is signal-to-noise (SNR), where the noise term also includes residual pre- and post-cursor ISI.
In general, statistical Rx adaptation will proceed as follows:
An initial CTLE setting is selected
A VGA setting is chosen such that the pulse amplitude falls within target bounds
The Rx FFE is automatically adjusted so that ISI at data sample points is minimized.
The DFE is adapted to remove post-cursor ISI.
SNR at data sample points is evaluated.
Steps above are repeated for each possible CTLE setting, keeping track of SNR values for each setting. The setting with the highest SNR is chosen as the global adaptation point.
Visit the Stimulus block mask dialog and change number of symbols to 4000.
Visit the export tab of the IBIS-AMI Manager and update the Rx ignore bits to 2000. This and the previous modification will ensure that the time domain adaptation has ample time to converge. A larger number of symbols and ignore time will yield more realistic results.
Run the model to simulate the ADC-based SerDes system.
In the example the ADC quantization is set to 6b, by default. Try changing the ADC quantization to a lower amount, observe how the time-domain eye shape is affected by reduced ADC precision.
The final part of this example takes the customized ADC-based SerDes Simulink model and then generates an IBIS-AMI compliant model: including model executables, IBIS and AMI files.
The current IBIS AMI standard does not have native support for ADC-based SerDes. The current standard is written for slicer-based SerDes, which contain a signal node wherein the equalized signal waveform is observed. In a slicer-based SerDes this node exists inside the DFE, right before the decision sampler. A continuous analog waveform is observable at that node, which includes the effect of all the upstream equalizers (such as CTLE) and the equalization due to DFE, as tap weighted and fed back prior decisions. Such a summing node does not exist in an ADC-based SerDes, due to the ADC in the system. In a real ADC-based SerDes system the ADC proves a vertical slice though the eye at the sampling instant. To emulate a virtual node, a time-agnostic ADC is used. This ADC quantizes each point in the incoming analog waveform at the simulation time-step rate: i.e. 1/fB/SPS, where SPS is the number of samples per symbol, and fB is the baud-rate. The Rx FFE also processes the input signal as a continuous waveform, rather than as samples. However, the Rx FFE applies a single tap values for SPS-simulation time-steps. The DFE is the stock DFE from the SerDes Toolbox and is written for slicer based SerDes. This signal chain allows for the signal integrity simulator to be able to observe a virtual eye in an ADC-based system.
Open the Export tab in the SerDes IBIS-AMI manager dialog box.
Verify that Dual model is selected for both the Tx and the Rx AMI Model Settings. This will create model executables that support both statistical (Init) and time domain (GetWave) analysis.
Set the Tx model Bits to ignore value to 5 since there are three taps in the Tx FFE.
Set the Rx model Bits to ignore value to 20,000 to allow sufficient time for the Rx DFE taps to settle during time domain simulations.
Set Models to export as Both Tx and Rx so that all the files are selected to be generated (IBIS file, AMI files and DLL files).
Press the Export button to generate models in the Target directory.