UCIe 1.0 Compliance Kit

This example shows you how to implement a Universal Chiplet Interconnect Express (UCIe) Version 1.0 (Specification Revision 1.1) interface for pre-layout analysis or post-layout verification using Parallel Link Designer from Signal Integrity Toolbox™.

This UCIe signal integrity compliance kit includes transfer nets, mask compliance checks, waveform processing levels and generic IBIS-AMI models for a UCIe interface. This includes generic buffer models for the UCIe transmitter and receiver. You can modify the kit to match your specific design implementation and perform complete pre-layout solution space analysis and/or full post-layout verification for waveform quality and compliance margins.

openSignalIntegrityKit("UCIe_1p1_Std_Pkg");