射频与混合信号

RF、SerDes 和混合信号系统建模和仿真

您可以使用以下 Simulink^® 产品以更高的速度和保真度对射频 (RF)、串行器/解串器 (SerDes) 和混合信号系统进行建模和仿真。

RF Blockset 可用于在不同抽象层次上对射频元素进行建模并仿真射频收发机和前端。您可以表征射频模型以进行自适应架构建模，包括 AGC、DPD 算法和波束成形。RF Blockset 还使您能够隐藏模型实现细节。
SerDes Toolbox 可用于对 SerDes 系统进行建模并为高速数字互连生成 IBIS-AMI 模型。您可以观察 ISI、抖动、噪声、插入损耗和串扰的影响，并验证通道是否符合 IEEE 802.3、OIF、PCle、USB 和 DDR5 等行业标准。
Mixed-Signal Blockset 可用于对 ADC、DAC、PLL、SMPS 系统进行建模。您还可以验证混合信号 IC，并将模拟电路行为与数字模型进行组合，以创建更详细的电子系统表示。

主题

Getting Started with RF Modeling (RF Blockset)
Build a simple RF receiver and perform circuit envelope simulation.
Design SerDes System and Export IBIS-AMI Model (SerDes Toolbox)
Create and analyze a SerDes system, and export an IBIS-AMI model using the SerDes Designer app.
Design and Evaluate Simple PLL Model (Mixed-Signal Blockset)
This example shows how to design a simple phase-locked loop (PLL) using a reference architecture and validate it using PLL Testbench.

精选示例

Top-Down Design of RF Receiver

Design an RF receiver for a ZigBee-like application using a top-down methodology.

Power Amplifier and DPD Modeling for Dynamic EVM Measurement

Extract a PA model using measured data, verify the quality of the fitting, and simulate the PA model with and without DPD.

Enable Model Protection and Accelerator Modes in RF Blockset Models

Conceal implementation details and enable accelerator modes in your RF Blockset model.

Architectural 112G PAM4 ADC-Based SerDes Model

Model a 112G PAM4 time-interleaved ADC-Based SerDes.

PCIe6 Transmitter/Receiver IBIS-AMI Model

Create IBIS-AMI models for a PCI-Express Generation 6 (PCIe Gen6) transmitter and receiver using the library blocks in SerDes Toolbox™. The IBIS-AMI models generated by this example can be used in Serial Link Designer from Signal Integrity Toolbox™ and conform to the PCIe Gen6 Base-Specification published by the PCI-SIG.

USB4 V2 Transmitter/Receiver IBIS-AMI Model

Implement USB4 V2 (80Gbps PAM3) Transmitter and Receiver architectures with SerDes Designer and generate IBIS-AMI models using the library blocks in SerDes Toolbox™. The generated models conform to the IBIS-AMI and USB4 V2 specifications.

Design and Evaluate Successive Approximation ADC Using Stateflow

Design and evaluate a 12-bit successive approximation register ADC.

Boost Power Train Design Workflow

Design a power supply with a boost power train for a specific operating point, control the output voltage, and perform time-domain simulations.

Digital Phase Locked Loop

Model a digital phase locked loop using the Mixed-Signal Blockset™. In a digital phase locked loop, phase detection is performed by a time to digital converter (TDC), loop filtering is performed by a digital filter, and the oscillator is a digitally controlled oscillator (DCO). This example demonstrates a behavioral model of a TDC, using the BiquadFilter from the DSP System Toolbox™ as the digital loop filter, and using VCOs and DACs from the Mixed-Signal Blockset to model the DCO.