基于 DO-254 标准检查模型合规性

您可以运行模型顾问来检查您的模型或子系统是否符合 DO-254 安全标准的选定方面。

要检查是否符合 DO 标准，请打开模型顾问，并运行 By Task > Modeling Standards for DO-254 下面的检查。

有关机载系统和设备审定中 DO-254 软件注意事项及相关标准的信息，请参阅航空无线电技术委员会 (RTCA)。

下表列出了 DO-254 的检查项。

DO-254 检查
Display model version information
Identify disabled library links
Identify parameterized library links
Identify unresolved library links
Check for model reference configuration mismatch (Simulink Coder)
Identify requirement links that specify invalid locations within documents (Simulink Requirements)
Identify requirement links with missing documents (Simulink Requirements)
Identify requirement links with path type inconsistent with preferences (Simulink Requirements)
Identify selection-based links having descriptions that do not match their requirements document text (Simulink Requirements)

以下是适用于 DO-178C/DO-331 标准的高完整性系统建模检查。

用于高完整性系统建模的模型检查

您可以运行模型顾问来检查您的模型或子系统是否符合高完整性系统模型安全标准的选定方面。

要检查是否符合高完整性系统模型标准，请从 By Task > Modeling Standards for DO-254 > High-Integrity Systems 运行高完整性检查：

下表列出了高完整性系统模型检查及其对应的支持 DO-254 安全标准的建模规范。有关高完整性建模规范的详细信息，请参阅高完整性系统建模。

高完整性系统模型检查	适用的高完整性系统建模规范
Check for inconsistent vector indexing methods	hisl_0021: Consistent vector indexing method
Check for variant blocks with 'Generate preprocessor conditionals' active	hisl_0023: Verification of variant blocks
Check for root Inports with missing properties	hisl_0024: Inport interface definition
Check for Relational Operator blocks that equate floating-point types	hisl_0017: Usage of blocks that compute relational operators (2)
Check usage of Relational Operator blocks	hisl_0016: Usage of blocks that compute relational operators
Check usage of Logical Operator blocks	hisl_0018: Usage of Logical Operator block
Check sample time-dependent blocks	hisl_0007: Usage of For Iterator or While Iterator subsystems
Check safety-related block reduction optimization settings	hisl_0046: Configuration Parameters > Simulation Target > Block reduction
Check usage of Abs blocks	hisl_0001: Usage of Abs block
Check usage of Assignment blocks	hisl_0029: Usage of Assignment blocks
Check for root Inports with missing range definitions	hisl_0025: Design min/max specification of input interfaces
Check for root Outports with missing range definitions	hisl_0026: Design min/max specification of output interfaces
Check Stateflow charts for transition paths that cross parallel state boundaries	hisf_0013: Usage of transition paths (crossing parallel state boundaries)
Check Stateflow charts for ordering of states and transitions	hisf_0002: User-specified state/transition execution order
Check Stateflow debugging options	hisf_0011: Stateflow debugging settings
Check Stateflow charts for uniquely defined data objects	hisl_0061: Unique identifiers for clarity
Check usage of shift operations for Stateflow data	hisf_0064: Shift operations for Stateflow data to improve code compliance
Check Stateflow charts for unary operators	hisf_0211: Protect against use of unary operators in Stateflow Charts to improve code compliance
Check for Strong Data Typing with Simulink I/O	hisf_0009: Strong data typing (Simulink and Stateflow boundary)
Check MATLAB Code Analyzer messages	himl_0004: MATLAB Code Analyzer recommendations for code generation
Check safety-related model referencing settings	hisl_0037: Configuration Parameters > Model Referencing
Check safety-related diagnostic settings for parameters	hisl_0302: Configuration Parameters > Diagnostics > Data Validity > Parameters
Check safety-related diagnostic settings for type conversions	hisl_0309: Configuration Parameters > Diagnostics > Type Conversion
Check safety-related diagnostic settings for signal connectivity	hisl_0306: Configuration Parameters > Diagnostics > Connectivity > Signals
Check safety-related diagnostic settings for bus connectivity	hisl_0307: Configuration Parameters > Diagnostics > Connectivity > Buses
Check safety-related diagnostic settings for model initialization	hisl_0304: Configuration Parameters > Diagnostics > Data Validity > Model initialization
Check safety-related diagnostic settings for model referencing	hisl_0310: Configuration Parameters > Diagnostics > Model Referencing
Check safety-related diagnostic settings for saving	hisl_0036: Configuration Parameters > Diagnostics > Saving
Check safety-related diagnostic settings for Stateflow	hisl_0311: Configuration Parameters > Diagnostics > Stateflow
Check model object names	hisl_0032: Model object names
Check for model elements that do not link to requirements	hisl_0070: Placement of requirement links in a model
Check for inappropriate use of transition paths	hisf_0014: Usage of transition paths (passing through states)
Check usage of Bitwise Operator block	hisl_0019: Usage of bitwise operations
Check data types for blocks with index signals	hisl_0022: Data type selection for index signals
Check model file name	hisl_0031: Model file names
Check if/elseif/else patterns in MATLAB Function blocks	himl_0006: MATLAB code if / elseif / else patterns
Check switch statements in MATLAB Function blocks	himl_0007: MATLAB code switch / case / otherwise patterns
Check global variables in graphical functions	hisl_0062: Global variables in graphical functions
Check for length of user-defined object names	hisl_0063: Length of user-defined object names to improve MISRA C:2012 compliance
Check usage of conditionally executed subsystems	hisl_0012: Usage of conditionally executed subsystems
Check usage of standardized MATLAB function headers	himl_0001: Usage of standardized MATLAB function headers
Check usage of relational operators in MATLAB Function blocks	himl_0008: MATLAB code relational operator data types
Check usage of equality operators in MATLAB Function blocks	himl_0009: MATLAB code with equal / not equal relational operators
Check usage of logical operators and functions in MATLAB Function blocks	himl_0010: MATLAB code with logical operators and functions
Check naming of ports in Stateflow charts	hisf_0016: Stateflow port names
Check scoping of Stateflow data objects	hisf_0017: Stateflow data object scoping
Check usage of Gain blocks	hisl_0066: Usage of Gain blocks
Check usage of bitwise operations in Stateflow charts	hisf_0003: Usage of bitwise operations
Check data type of loop control variables	hisl_0102: Data type of loop control variables to improve MISRA C:2012 compliance

HDL Code Advisor 检查

HDL Coder™ 中的 HDL Code Advisor 和模型顾问检查验证并更新您的 Simulink^® 模型或子系统，以确保与 HDL 代码生成的兼容性。Code Advisor 检查以下内容：

模型配置设置
端口和子系统设置
模块和模块设置
本机浮点支持
行业标准规范

下表列出了由 DO-254 安全标准支持的 HDL Code Advisor 检查：

HDL Code Advisor 检查	说明
Check for infinite and continuous sample time sources (HDL Coder)	检查具有连续采样时间的源模块。
Check for unsupported blocks (HDL Coder)	检查 HDL 代码生成不支持的模块。
Check for large matrix operations (HDL Coder)	检查大型矩阵运算。
Identify unconnected lines, input ports, and output ports	检查未连接的信号线或端口。
Identify disabled library links	搜索模型中禁用的库链接。
Identify unresolved library links	搜索模型中未解析的库链接，未解析的库链接会导致找不到指定的库模块。
Check for MATLAB Function block settings (HDL Coder)	检查 MATLAB Function 模块的 HDL 兼容设置。
Check for Stateflow chart settings (HDL Coder)	检查 Stateflow^® Chart 模块的 HDL 兼容设置。
Check Delay, Unit Delay and Zero-Order Hold blocks for rate transition	识别用于速率转换的 Delay、Unit Delay 或 Zero-Order Hold 模块。用实际 Rate Transition 模块替换这些模块。
Check for unsupported storage class for signal objects (HDL Coder)	检查信号对象存储类是 `'ExportedGlobal'`、`'ImportedExtern'` 还是 `'ImportedExternPointer'`
Check file extension (HDL Coder)	检查包含实体的 VHDL 文件的文件扩展名。
Check naming conventions (HDL Coder)	检查 EDA 工具使用的标准关键字。
Check top-level subsystem/port names (HDL Coder)	检查顶层模块/实体和端口名称。
Check module/entity names (HDL Coder)	检查模块/实体名称。
Check signal and port names (HDL Coder)	检查信号和端口名称长度。
Check package file names (HDL Coder)	检查包含包的文件名。
Check generics (HDL Coder)	检查顶层子系统的泛型。
Check clock, reset, and enable signals (HDL Coder)	检查时钟、重置和使能信号的命名约定。
Check architecture name (HDL Coder)	检查生成的 HDL 代码中的 VHDL 架构名称。
Check entity and architecture (HDL Coder)	检查 VHDL 实体和架构是否在同一文件中说明。
Check clock settings (HDL Coder)	检查对时钟信号的限制。
Check model for foreign characters	搜索模型中未解析的库链接，未解析的库链接会导致找不到指定的库模块。
Check for global reset setting for Xilinx and Altera devices (HDL Coder)	检查 Altera^® 设备的异步重置设置和 Xilinx^® 设备的同步重置设置。
Check inline configurations setting (HDL Coder)	检查您是否启用了 `InlineConfigurations`。
Check algebraic loops (HDL Coder)	检查模型中是否存在代数环。
Check for visualization settings (HDL Coder)	检查模型的显示设置：端口数据类型和采样时间颜色编码。
Check delay balancing setting (HDL Coder)	检查是否启用了 Balance Delays。
Check for model parameters suited for HDL code generation (HDL Coder)	检查是否为 HDL 代码生成设置了模型参数。
Check for double datatypes in the model with Native Floating Point (HDL Coder)	检查模型中的 `double` 数据类型。
Check for Data Type Conversion blocks with incompatible settings (HDL Coder)	检查 Data Type Conversion 模块的转换模式。
Check for HDL Reciprocal block usage (HDL Coder)	检查 HDL Reciprocal 模块是否未使用浮点类型。
Check for Relational Operator block usage (HDL Coder)	检查使用浮点类型的 Relational Operator 模块是否具有布尔输出。
Check for unsupported blocks with Native Floating Point (HDL Coder)	检查不支持使用本机浮点的模块。
Check for blocks that have nonzero output latency (HDL Coder)	检查使用本机浮点且具有非零输出延迟的模块。
Check blocks with nonzero ulp error (HDL Coder)	检查使用本机浮点且具有非零 ulp 错误的模块。
Check for single datatypes in the model (HDL Coder)	检查模型中的 `single` 数据类型。
Check initial conditions of enabled and triggered subsystems (HDL Coder)	检查使能触发子系统的初始条件。
Check for invalid top level subsystem (HDL Coder)	检查对于 HDL 代码生成来说不能在顶层的子系统。

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