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Functional Requirements Testing

Generate test cases for functional design requirements


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Test ConditionConstrain signal values in test cases
Test ObjectiveDefine custom objectives that signals must satisfy in test cases
DetectorDetect true duration on input and construct output true duration based on output type
ExtenderExtend true duration of input
ImpliesSpecify condition that produces a certain response
Within ImpliesVerify response occurs within desired duration
Verification SubsystemSpecify proof or test objectives without impacting simulation results or generated code


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sldvoptionsCreate design verification options object
sldv.conditionTest condition function for Stateflow charts and MATLAB Function blocks
sldv.testTest objective function for Stateflow charts and MATLAB Function blocks
sldvextractExtract subsystem or subchart contents into new model for analysis
sldvtimerIdentify, change, and display timer optimizations
sldvoptionsCreate design verification options object
sldvrunAnalyze model
sldvlogsignalsLog simulation input port values
sldvgencovAnalyze models to obtain missing model coverage
sldvruntestSimulate model by using input data
sldvruntestoptsGenerate simulation or execution options for sldvruntest or sldvruncgvtest
sldvharnessoptsDefault options for sldvmakeharness
sldvmakeharnessGenerate harness model
sldvmergeharnessMerge test cases and initializations into one harness model
sldvreportGenerate Simulink Design Verifier report
sldvchecksumReturns checksum of model


Introduction to Test Case Generation

Component Verification

Parameter Configuration

Simulink Design Verifier Pane