Verify Multiple Conditions at a Time

To verify multiple conditions in a single time step, include verify statements inside if statements, and include multiple if statements in a single test step.

For example, suppose you have a simple two-button utility function that operates as exclusive-or logic. More than one of the following conditions can be valid at the same time step.

Condition	Expected Output
`RedButtonIN == false && GreenButtonIN == false`	`RedButtonOUT == false && GreenButtonOUT == false`
`GreenButtonIN == false`	`GreenButtonOUT ~= true`
`RedButtonIN == false`	`RedButtonOUT ~= true`
`RedButtonIN == true && GreenButtonIN == true`	`RedButtonOUT == false && GreenButtonOUT == false`
`RedButtonIN == true && GreenButtonIN == false`	`RedButtonOUT == true && GreenButtonOUT == false`
`RedButtonIN == false && GreenButtonIN == true`	`RedButtonOUT == false && GreenButtonOUT == true`

To assess these conditions, this Test Assessment block includes six verify statements in the first test step, contained in if statements. The test step is active during simulation, and the if statements are evaluated at each time step.

Test Assessment block verify statements

Verify Multiple Conditions at a Time

See Also