soc.sdk.MemorySystem Class

Name of the memory system, specified as a character vector.

Example: 'MyMemorySystem'

Attributes:

Data Types: char

Tcl file that implements the memory system in the chosen synthesis tool project, specified as a string of characters. The string must represent a valid file name in your installation and it may include $(TARGET_ROOT) token. The default is ''.

Attributes:

Data Types: char

Constraints file for implements the memory system in the chosen synthesis tool project, specified as a string of characters. The string must represent a valid file name in your installation and it may include $(TARGET_ROOT) token. The default is ''.

Attributes:

Data Types: char

The name of the slave interface port, specified as a string of displayable characters. The default is ''.

Attributes:

Data Types: char

The name of the slave interface reset port, specified as a string of displayable characters. The default is ''.

Attributes:

Data Types: char

The slave interface data width, specified as an N-length vector consisting of the supported data widths. When unspecified, the default list is [32 64 128 256 512 1024].

Attributes:

Data Types: double

The default value can be any value in the SlaveInterfaceDataWidth property list. When unspecified, the default value is the first value of the list.

Attributes:

Data Types: double

The slave interface frequency, specified as a numerical value. Units are in MHz. The default is 200.

Attributes:

Data Types: double

The name of the clock output port, specified as a string of displayable characters. The default is ''.

Attributes:

Data Types: char

The name of the reset output port, specified as a string of displayable characters. The default is ''.

Attributes:

Data Types: char

Specify first read latency as the number of clock cycles elapsed from the address phase to the first data transfer for the memory controller transactions, specified as a vector of the min and the max values. The default range is [0 100].

Attributes:

Data Types: double

Specify the default value of the first write transfer latency between the FirstWriteLatencyMinMax range. When not specified, the default value is the max value of the range.

Attributes:

Data Types: double

Specify the last write latency as the number of elapsed clock cycles from the last data transfer to completion of the transaction, including any turn-around time, specified as a vector of the min and the max values. The default range is [0 100].

Attributes:

Data Types: double

Specify the default value of the last write transfer latency between the LastWriteLatencyMinMax range. When not specified, the default value is the max value of the range.

Attributes:

Data Types: double

Specify the first read latency as the number of clock cycles elapsed from the address phase to the first data transfer for the memory controller transactions, specified as a vector of the min and the max values. The default range is [0 100].

Attributes:

Data Types: double

Specify the default value of first read latency between the FirstReadLatencyMinMax range. The default value is the max value of the range.

Attributes:

Data Types: double

Specify the last read latency range as the number of elapsed clock cycles from the last data transfer to completion of the transaction, including any turn-around time, as a vector consisting of the min and the max values. The default range is [0 100].

Attributes:

Data Types: double

Specify the default value of last read latency between the LastReadLatencyMinMax range. The default value is the max value of the range.

Attributes:

Data Types: double