STATCOM Phasor Model

Description

The Static Synchronous Compensator (STATCOM) is one of the key FACTS devices. Based on a voltage-sourced converter, the STATCOM regulates system voltage by absorbing or generating reactive power. Contrary to a thyristor-based Static Var Compensator (SVC), STATCOM output current (inductive or capacitive) can be controlled independent of the AC system voltage.

The power grid consists of two 500-kV equivalents (respectively 3000 MVA and 2500 MVA) connected by a 600-km transmission line. When the STATCOM is not in operation, the "natural" power flow on the transmission line is 930 MW from bus B1 to B3. The STATCOM is located at the midpoint of the line (bus B2) and has a rating of +/- 100MVA. This STATCOM is a phasor model of a typical three-level PWM STATCOM. If you open the STATCOM dialog box and select "Display Power data", you will see that our model represents a STATCOM having a DC link nominal voltage of 40 kV with an equivalent capacitance of 375 uF. On the AC side, its total equivalent impedance is 0.22 pu on 100 MVA. This impedance represents the transformer leakage reactance and the phase reactor of the IGBT bridge of an actual PWM STATCOM.

Simulation

1. STATCOM Dynamic Response

We will now verify the dynamic response of our model. Open the STATCOM dialog box and select "Display Control parameters". Verify that the "Mode of operation" is set to "Voltage regulation" and that "External control of reference voltage Vref" is selected. Also, the "droop" parameter should be set to 0.03 and the "Vac Regulator Gains" to 5 (proportional gain Kp) and 1000 (integral gain Ki). Close the STATCOM dialog block and open the "Step Vref" block (the red timer block connected to the "Vref" input of the STATCOM). This block should be programmed to modify the reference voltage Vref as follows: Initially Vref is set to 1 pu; at t=0.2 s, Vref is decreased to 0.97 pu; then at t=0.4 s, Vref is increased to 1.03; and finally at 0.6 s, Vref is set back to 1 pu. Also, make sure that the fault breaker at bus B1will not operate during the simulation (the parameters "Switching of phase A, B and C" should not be selected).

Run the simulation and look at the "VQ_STATCOM" scope. The first graph displays the Vref signal (magenta trace) along with the measured positive-sequence voltage Vm at the STATCOM bus (yellow trace). The second graph displays the reactive power Qm (yellow trace) absorbed (positive value) or generated (negative value) by the STATCOM. The signal Qref (magenta trace) is not relevant to our simulation because the STATCOM is in "Voltage regulation" and not in "Var Control".

Looking at the Qm signal we can determine that the closed-loop time constant of the system is about 20 ms. This time constant depends primarily on the power system strength at bus B2 and on the programmed Vac Regulator gains of the STATCOM. To see the impact of the regulator gains, multiply the two gains of the Vac Regulator Gains by two and rerun the simulation. You should observe a much faster response with a small overshoot.

Looking at the Vm and Vref signals, you can see that the STATCOM does not operate as a perfect voltage regulator (Vm does not follow exactly the reference voltage Vref). This is due to the regulator droop (regulating slope) of 0.03 pu. For a given maximum capacitive/inductive range, this droop is used to extend the linear operating range of the STATCOM and also to ensure automatic load sharing with other voltage compensators (if any). Set the droop parameter to 0 and the voltage regulator gains back to 5 (Kp) and 1000 (Ki). If you then run a simulation, you will see that the measured voltage Vm now follows perfectly the reference voltage Vref.

2. STATCOM compared to a SVC under fault condition

We will now compare our STATCOM model with a SVC model having the same rating (+/- 100 MVA). If you double-click on the "SVC Power System" (the magenta block), you will see a SVC connected to a power grid similar to the power grid on which our STATCOM is connected. A remote fault will be simulated on both systems using a fault breaker in series with a fault impedance. The value of the fault impedance has been programmed to produce a 30% voltage sag at bus B2. Before running the simulation, you will first disable the "Step Vref" block by multiplying the time vector by 100. You will then program the fault breaker by selecting the parameters "Switching of phase A, B and C" and verify that the breaker is programmed (look at the "Transition times" parameter) to operate at t=0.2 s for a duration of 10 cycles. Check also that the fault breaker inside the "SVC Power System" has the same parameters. Finally, set the STATCOM droop back to its original value (0.03 pu).

Run the simulation and look at the "SVC vs STATCOM" scope. The first graph displays the measured voltage Vm on both systems (magenta trace for the SVC). The second graph displays the measured reactive power Qm generated by the SVC (magenta trace) and the STATCOM (yellow trace). During the 10-cycle fault, a key difference between the SVC and the STATCOM can be observed. The reactive power generated by the SVC is -0.48 pu and the reactive power generated by the STATCOM is -0.71 pu. We can then see that the maximum capacitive power generated by a SVC is proportional to the square of the system voltage (constant susceptance) while the maximum capacitive power generated by a STATCOM decreases linearly with voltage decrease (constant current). This ability to provide more capacitive power during a fault is one important advantage of the STATCOM over the SVC. In addition, the STATCOM will normally exhibits a faster response than the SVC because with the voltage-sourced converter, the STATCOM has no delay associated with the thyristor firing (in the order of 4 ms for a SVC).