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aximaster

Read and write memory locations on an FPGA board from MATLAB

Description

The aximaster object communicates with the MATLAB® AXI master IP when it is running on an FPGA board. The object forwards read and write commands to the IP to access slave memory locations on the FPGA board. Before using this object, follow the steps in Set Up for MATLAB AXI Master.

Construction

mem = aximaster(vendor) returns an object, mem, that controls an AXI4 master IP for the FPGA vendor that is running on your board. This connection enables you to access memory locations in an SoC design from MATLAB.

mem = aximaster(vendor,Name,Value, ...) returns an object, mem, with additional properties specified by one or more Name,Value pair arguments.

Input Arguments

expand all

Specify the manufacturer of your FPGA board. The AXI master IP varies depending on the type of FPGA you have.

Properties

expand all

Specify this property if more than one JTAG cable of the same type are connected to the host computer. If the host computer has more than one JTAG cable and you do not specify this property, the object returns an error. The error message contains the names of the available JTAG cables. See Select from Multiple JTAG Cables.

Specify the interface type for communicating between the host and the FPGA.

Specify the IP address of the Ethernet port on the FPGA board.

To enable this property, set Interface to UDP.

Example: 192.168.0.10

Specify the UDP port value of the target FPGA as an unsigned 16-bit integer.

To enable this property, set Interface to UDP.

Example: 12345

Specify the JTAG clock frequency, in MHz. For Intel® FPGAs the JTAG clock frequency is 12 or 24 MHz. For Xilinx® FPGAs, the JTAG clock frequency is 33 or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.

Methods

readmemoryRead data out of AXI4 memory-mapped slaves
releaseRelease JTAG cable resource
writememoryWrite data to AXI4 memory-mapped slaves

Examples

Access Memory on the FPGA Board from MATLAB

To use this object, you must have a design running on an FPGA board connected to the MATLAB host machine. The FPGA design must include an AXI master IP customized for your FPGA vendor. This IP is included with the support package installation. For how to include the IP in your project, see Access FPGA External Memory Using MATLAB as AXI Master.

Create a MATLAB AXI master object. The object connects with the FPGA board and confirms that the IP is present.

mem = aximaster('Altera')
mem = 

  aximaster with properties:

           Vendor: 'Altera'
    JTAGCableName: 'auto'

Write and read one or more addresses with one command. By default, the commands auto-increment the address for each word of data. For instance, write ten addresses. Then read from a single location.

writememory(mem,140,[10:19])
rd_d = readmemory(mem,140,1)
rd_d =

  uint32

   10

Or, read from ten locations.

rd_d = readmemory(mem,140,10)
rd_d =

  1×10 uint32 row vector

   10   11   12   13   14   15   16   17   18   19

Set the BurstType property to 'Fixed' to turn off the auto-increment and access the same address multiple times. For instance, read ten times from the same address.

rd_d = readmemory(mem,140,10,'BurstType','Fixed')
rd_d =

  1×10 uint32 row vector

   10   10   10   10   10   10   10   10   10   10

Write ten times to the same address. Note that the final value stored in address 140 is 29.

writememory(mem,140,[20:29],'BurstType','Fixed')
rd_d = readmemory(mem,140,10)
rd_d =

  1×10 uint32 row vector

   29   11   12   13   14   15   16   17   18   19

Alternatively, specify the address as a hexadecimal string. To cast the read data to a data type other than uint32, use the OutputDataType property.

writememory(mem,'1c',[0:4:64])
rd_d = readmemory(mem,'1c',16,'OutputDataType',numerictype(0,6,4))
rd_d = 

  Columns 1 through 10
         0    0.2500    0.5000    0.7500    1.0000    1.2500    1.5000    1.7500    2.0000    2.2500
  Columns 11 through 16
    2.5000    2.7500    3.0000    3.2500    3.5000    3.7500

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 6
        FractionLength: 4

When you no longer need to access the board, release the JTAG connection.

release(mem)

Select from Multiple JTAG Cables

If two cables of the same type are connected to your host computer, specify the JTAGCableName identifier for the board where the JTAG master IP is running. To see the JTAG cable identifiers, attempt to create an aximaster object. The object returns a list of the current JTAG cable names.

h = aximaster('Xilinx')
Error using fpgadebug_mex
Found more than one JTAG cable:
0 (JtagSmt1): #tpt_0001#ptc_0002#210203991642
1 (Arty): #tpt_0001#ptc_0002#210319789795
Please disconnect the extra cable, or specify the cable name as an input argument.
See documentation of FPGA Data Capture or MATLAB as AXI master to learn how to set
the cable name.
To communicate with the Arty board, specify the matching JTAG cable name.
h = aximaster('Xilinx','JTAGCableName','#tpt_0001#ptc_0002#210319789795')

Introduced in R2017a