Read data out of AXI4 memory-mapped slaves
data = readmemory(mem,addr,size)
data = readmemory(mem,addr,size,Name,Value)
data = readmemory(mem,addr,size) reads
locations of data starting from the address specified in
incrementing the address for each word. The object casts the data to
uint64 (depending on the data-size
aximaster IP). The address,
refer to an AXI slave memory location controlled by the AXI master IP on your FPGA
manages the connection between MATLAB® and the AXI master IP.
mem— Connection to AXI master IP on FPGA board
object™ that you created and configured.
addr— Starting address for read operation
Specify an integer or a hexadecimal character vector. The object casts the address to
uint64, depending on the
AXI master IP address width. The address must refer to an AXI slave memory
location controlled by the AXI master IP on your FPGA board.
size— Number of locations to read
Number of memory locations to read, specified as an integer.
By default, the object reads from a contiguous address block, incrementing
the address for each operation. To turn off address increment mode
and read repeatedly from the same location, set the
When you specify a large operation size, such as reading a block of DDR memory, the object automatically breaks the operation into multiple bursts, using the maximum supported burst size. The maximum supported burst size is 256 words.
BurstType— AXI4 burst type
'Increment' mode, the AXI master reads
a vector of data from contiguous memory locations, starting with the
specified address. In
'Fixed' mode, the AXI master
reads all data from the same address.
OutputDataType— Data type assigned to read data
'uint64'(default) | |
The object casts the data read out of the FPGA to the specified data type.
To use this object, you must have a design running on an FPGA board connected to the MATLAB host machine. The FPGA design must include an AXI master IP customized for your FPGA vendor. This IP is included with the support package installation. For how to include the IP in your project, see Access FPGA External Memory Using MATLAB as AXI Master.
Create a MATLAB AXI master object. The object connects with the FPGA board and confirms that the IP is present.
mem = aximaster('Altera')
mem = aximaster with properties: Vendor: 'Altera' JTAGCableName: 'auto'
Write and read one or more addresses with one command. By default, the commands auto-increment the address for each word of data. For instance, write ten addresses. Then read from a single location.
writememory(mem,140,[10:19]) rd_d = readmemory(mem,140,1)
rd_d = uint32 10
Or, read from ten locations.
rd_d = readmemory(mem,140,10)
rd_d = 1×10 uint32 row vector 10 11 12 13 14 15 16 17 18 19
BurstType property to
'Fixed' to turn off
the auto-increment and access the same address multiple times. For instance, read ten times from
the same address.
rd_d = readmemory(mem,140,10,'BurstType','Fixed')
rd_d = 1×10 uint32 row vector 10 10 10 10 10 10 10 10 10 10
Write ten times to the same address. Note that the final value stored in address
writememory(mem,140,[20:29],'BurstType','Fixed') rd_d = readmemory(mem,140,10)
rd_d = 1×10 uint32 row vector 29 11 12 13 14 15 16 17 18 19
Alternatively, specify the address as a hexadecimal string. To cast the read data to a data
type other than
uint32, use the
writememory(mem,'1c',[0:4:64]) rd_d = readmemory(mem,'1c',16,'OutputDataType',numerictype(0,6,4))
rd_d = Columns 1 through 10 0 0.2500 0.5000 0.7500 1.0000 1.2500 1.5000 1.7500 2.0000 2.2500 Columns 11 through 16 2.5000 2.7500 3.0000 3.2500 3.5000 3.7500 DataTypeMode: Fixed-point: binary point scaling Signedness: Unsigned WordLength: 6 FractionLength: 4
When you no longer need to access the board, release the JTAG connection.