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release

Release JTAG cable resource

Syntax

release(mem)

Description

release(mem) releases the JTAG cable resource, freeing the cable for use to reprogram the FPGA. After initialization, the AXI master object, mem, holds the JTAG cable resource, and other programs cannot access the JTAG cable. While you have an active AXI master object, FPGA programming over JTAG fails. Call the release method before reprogramming the FPGA.

Input Arguments

expand all

Specify an aximaster System object™ that you created and configured.

Examples

Access Memory on the FPGA Board from MATLAB

To use this object, you must have a design running on an FPGA board connected to the MATLAB® host machine. The FPGA design must include an AXI master IP customized for your FPGA vendor. This IP is included with the support package installation. For how to include the IP in your project, see Access FPGA External Memory Using MATLAB as AXI Master.

Create a MATLAB AXI master object. The object connects with the FPGA board and confirms that the IP is present.

mem = aximaster('Altera')
mem = 

  aximaster with properties:

           Vendor: 'Altera'
    JTAGCableName: 'auto'

Write and read one or more addresses with one command. By default, the commands auto-increment the address for each word of data. For instance, write ten addresses. Then read from a single location.

writememory(mem,140,[10:19])
rd_d = readmemory(mem,140,1)
rd_d =

  uint32

   10

Or, read from ten locations.

rd_d = readmemory(mem,140,10)
rd_d =

  1×10 uint32 row vector

   10   11   12   13   14   15   16   17   18   19

Set the BurstType property to 'Fixed' to turn off the auto-increment and access the same address multiple times. For instance, read ten times from the same address.

rd_d = readmemory(mem,140,10,'BurstType','Fixed')
rd_d =

  1×10 uint32 row vector

   10   10   10   10   10   10   10   10   10   10

Write ten times to the same address. Note that the final value stored in address 140 is 29.

writememory(mem,140,[20:29],'BurstType','Fixed')
rd_d = readmemory(mem,140,10)
rd_d =

  1×10 uint32 row vector

   29   11   12   13   14   15   16   17   18   19

Alternatively, specify the address as a hexadecimal string. To cast the read data to a data type other than uint32, use the OutputDataType property.

writememory(mem,'1c',[0:4:64])
rd_d = readmemory(mem,'1c',16,'OutputDataType',numerictype(0,6,4))
rd_d = 

  Columns 1 through 10
         0    0.2500    0.5000    0.7500    1.0000    1.2500    1.5000    1.7500    2.0000    2.2500
  Columns 11 through 16
    2.5000    2.7500    3.0000    3.2500    3.5000    3.7500

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 6
        FractionLength: 4

When you no longer need to access the board, release the JTAG connection.

release(mem)

Introduced in R2017a