Write data to AXI4 memory-mapped slaves
writememory(mem,addr,data) writes all words
data starting from the address specified
addr, and incrementing the address for each
word. The address,
addr, must refer to an AXI
slave memory location controlled by the AXI master IP on your FPGA
manages the connection between MATLAB® and the AXI master IP.
mem— Connection to AXI master IP on FPGA board
object™ that you created and configured.
addr— Starting address for write operation
Specify an integer or a hexadecimal character vector. The object casts the address to
uint64, according to the
AXI master IP address-width. The address must refer to an AXI slave memory
location controlled by the AXI master IP on your FPGA board.
data— Data words to write
By default, the object writes the data to a contiguous address
block, incrementing the address for each operation. To turn off address
increment mode and write each data value to the same location, set
BurstType property to
Before sending the write request to the FPGA, the object casts the input data to
int64. The type
conversion follows these rules:
If the input data is
double, then the data is
depending on the data-width of the AXI Master IP.
If the input data is
single, then the data is
depending in the AXI Master IP data width.
If the bit width of the input data type is less than the AXI Master data width, then the data is sign extended to the width of the AXI Master data width.
If the bit width of the input data type is longer than the AXI
Master data width, then the data is cast to
uint64. It is cast
to match the data width of the AXI Master IP and the signedness of
the original data type.
If the input data is a fixed-point data type, then the object writes the stored integer value of the data.
When you specify a large operation size, such as writing a block of DDR memory, the object automatically breaks the operation into multiple bursts, using the maximum supported burst size. The maximum supported burst size is 256 words.
BurstType— AXI4 burst type
'Increment' mode, the AXI
master writes a vector of data to contiguous memory spaces starting
with the specified address. In
the AXI master writes all data to the same address.
To use this object, you must have a design running on an FPGA board connected to the MATLAB host machine. The FPGA design must include an AXI master IP customized for your FPGA vendor. This IP is included with the support package installation. For how to include the IP in your project, see Access FPGA External Memory Using MATLAB as AXI Master.
Create a MATLAB AXI master object. The object connects with the FPGA board and confirms that the IP is present.
mem = aximaster('Altera')
mem = aximaster with properties: Vendor: 'Altera' JTAGCableName: 'auto'
Write and read one or more addresses with one command. By default, the commands auto-increment the address for each word of data. For instance, write ten addresses. Then read from a single location.
writememory(mem,140,[10:19]) rd_d = readmemory(mem,140,1)
rd_d = uint32 10
Or, read from ten locations.
rd_d = readmemory(mem,140,10)
rd_d = 1×10 uint32 row vector 10 11 12 13 14 15 16 17 18 19
BurstType property to
'Fixed' to turn off
the auto-increment and access the same address multiple times. For instance, read ten times from
the same address.
rd_d = readmemory(mem,140,10,'BurstType','Fixed')
rd_d = 1×10 uint32 row vector 10 10 10 10 10 10 10 10 10 10
Write ten times to the same address. Note that the final value stored in address
writememory(mem,140,[20:29],'BurstType','Fixed') rd_d = readmemory(mem,140,10)
rd_d = 1×10 uint32 row vector 29 11 12 13 14 15 16 17 18 19
Alternatively, specify the address as a hexadecimal string. To cast the read data to a data
type other than
uint32, use the
writememory(mem,'1c',[0:4:64]) rd_d = readmemory(mem,'1c',16,'OutputDataType',numerictype(0,6,4))
rd_d = Columns 1 through 10 0 0.2500 0.5000 0.7500 1.0000 1.2500 1.5000 1.7500 2.0000 2.2500 Columns 11 through 16 2.5000 2.7500 3.0000 3.2500 3.5000 3.7500 DataTypeMode: Fixed-point: binary point scaling Signedness: Unsigned WordLength: 6 FractionLength: 4
When you no longer need to access the board, release the JTAG connection.