To access on-board memory locations from MATLAB®, you must include the MATLAB AXI master IP in your FPGA design. This IP connects to slave memory locations on the board. The IP also responds to read and write commands from the MATLAB command line, over JTAG, PCI Express, or Ethernet cable.
To set up the AXI master IP for access from MATLAB, follow these setup steps:
Add the path for the AXI Master IP files to your project using the
Open Quartus®, and from the IP Catalog select the MATLAB AXI master IP in your FPGA design.
When using JTAG as a physical connection, select MATLAB as AXI Master.
When using Ethernet as a physical connection, select UDP Matlab as AXI Master and Ethernet MAC Hub and add them to your project.
When using PCIe as a physical connection, select PCIe MATLAB as AXI Master and add it to your project.
In your FPGA project, specify which addresses the AXI master IP is allowed to access.
The AXI master IP supports AXI4 Lite, AXI4, and Altera® Avalon slave memory locations. The FPGA interconnect automatically converts AXI4 transactions to the protocol of each address.
Compile your FPGA project, including the MATLAB AXI master IP.
Connect your FPGA board to your host computer using a physical cable (JTAG, PCI Express, or Ethernet cable).
Program the FPGA with your compiled design.
Alternatively, you can perform these steps in the HDL Coder™ guided workflow by using a sample reference design, such as the one included in this example: IP Core Generation Workflow Without an Embedded ARM Processor: Arrow DECA MAX 10 FPGA Evaluation Kit (HDL Coder).
Once the program is running on your FPGA board, you can create a MATLAB AXI master object. See
aximaster. To access the slave memory locations on the board, use the
writememory methods of this object.
When using JTAG as a physical connection to your board, you might have additional IPs that use
the same JTAG connection. Such IPs include FPGA data capture, Intel® SignalTap II, or Xilinx®
Vivado® Logic Analyzer cores. However, only one of these applications can use
the JTAG cable at a time. You must release the
aximaster object to return the JTAG resource for use by other
The most common conflicting use of the JTAG cable is to reprogram the FPGA. You must stop any FPGA data capture or MATLAB AXI master JTAG connection before you can use the cable to program the FPGA.
The maximum data rate between host computer and FPGA is limited by the JTAG clock frequency. For Intel boards, the JTAG clock frequency is 12 MHz.or 24 MHz. For Xilinx boards, the JTAG clock frequency is 33 MHz. or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.