Use this support package with these recommended versions:
Intel® Quartus® Prime 18.1
Intel Quartus Prime Pro 19.2 (supported for Intel Cyclone® 10 GX only)
Intel Quartus II 13.1 (supported for Intel Cyclone III boards only)
For tool setup instructions, see Set Up FPGA Design Software Tools (HDL Verifier).
You can run FPGA-in-the-loop, FPGA data capture, or MATLAB® AXI master over a JTAG cable to your board. However, each feature requires exclusive use of the JTAG cable, so you cannot run more than one feature at the same time. To allow other tools access to the JTAG cable, such as programming the FPGA, and Quartus SignalTap, you must discontinue the JTAG connection in MATLAB. To release the JTAG cable:
FPGA-in-the-loop — Close the Simulink® model, or call the
release method of the System
FPGA data capture — Close the FPGA Data Capture app, release the System object, or close the Simulink model.
MATLAB AXI master — Call the
release method of the object.
For Intel boards, the JTAG clock frequency is 12 or 24 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.
|Required Hardware||Required Software|
You can run FPGA-in-the-loop over an Ethernet connection.
|Required Hardware||Supported Interfaces||Required Software|
There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication.
FPGA-in-the-loop over a PCI Express® connection is supported only for 64-bit Windows operating systems.
Altera® Quartus II 15.0