Access on-board memory locations from MATLAB, using the MATLAB
AXI Master IP in your FPGA design, and the
The object connects to the IP over the JTAG cable, and allows read
and write commands to slave memory locations from the MATLAB command
|Read and write memory locations on an FPGA board from MATLAB|
High-level steps for accessing memory on an FPGA board from MATLAB
Integrate and configure Ethernet MATLAB as AXI Master using User Datagram Protocol (UDP).
Integrate and configure of MATLAB as AXI Master IP over PCI Express.