This example shows how to use MATLAB® AXI master over PCI Express® (PCIe) to access the external memory connected to an FPGA. The FPGA includes a Xilinx® DDR memory controller for accessing the DDR memory. This memory controller provides an AXI4 slave interface for write and read operations by other components in the FPGA. The PCIe MATLAB AXI master feature provides an AXI master object that you can use to access any memory mapped location in the FPGA. This example shows how to integrate PCIe MATLAB AXI master into a Xilinx Vivado® project and write and read data from the DDR memory using MATLAB.
Xilinx Vivado Design Suite, with supported version listed in Supported EDA Tools and Hardware
Xilinx Kintex® UltraScale+ FPGA KCU116 Evaluation Kit
HDL Verifier™ Support Package for Xilinx FPGA Boards
Host machine (PC) with PCIe slot
1. Set up the FPGA board. Connect the Xilinx KCU116 board to the host computer via PCIe and JTAG cables. The JTAG cable is used for programming the device.
2. Prepare the example in MATLAB. Set up the Xilinx Vivado tool path. Use your own Xilinx Vivado installation path when executing the command.
Create a Vivado project for this example. The following MATLAB command creates a Vivado project named
pcieaximaster.xpr and contains the IP Integrator block diagram and constraint files.
system('vivado -mode batch -source pcieAXIMcreateproject.tcl')
3. Configure the Vivado project with a Vivado IP. To use the PCIe MATLAB as AXI Master IP inside the Vivado IP Integrator, add the folder that contains the IP to the IP repository path setting for the Vivado project. Add the path to the project by executing this command in MATLAB.
Open the generated Vivado project in GUI mode by double-clicking the project in a file browser or by executing this command in MATLAB.
system('vivado pcieaximaster.xpr &')
4. Add PCIe MATLAB as AXI Master IP to the FPGA design. In the Vivado GUI, open the block diagram design file
pcieAXIMdesign_1.bd. You can find the design in the source file subwindow.
Set the address of
xdma_0 (AXI Bridge Subsystem for PCI Express) and
ddr4_0 (memory controller) as shown in this figure.
Alternatively, you can complete the above setup steps by executing Tcl commands in Vivado.
5. Generate the FPGA programming file and program the FPGA. Click Generate Bitstream on the Vivado window to generate the FPGA programming file. Vivado might prompt you to save the project before proceeding to the next step. Generating the bitstream file takes about 5 to 10 minutes for Vivado to generate the bitstream file.
After Vivado generates the bitstream, program the FPGA by executing this command in MATLAB.
6. Reboot the host machine after programming the FPGA.
Once the design is running on the FPGA board, you can write and read from the AXI slaves that are connected to the PCIe MATLAB as AXI Master IP. This example writes data to the DDR memory connected to the FPGA and then retrieves data into MATLAB.
Create the AXI master object in MATLAB.
h = aximaster('Xilinx','interface','pcie');
Write and read from the memory locations on the FPGA. The following two lines use the AXI master object h to write 100 to address 0 and then read from address 0 of the DDR memory.