C28x-MCPWM

R2026b

Configure MCPWM modules and assign MCPWM signals to GPIO pins. The MCPWM module replaces the traditional ePWM module on the F28E12x processor family.

The MCPWM X-BAR brings signals to the MCPWM modules. Specifically, the MCPWM X-BAR is connected to the Digital Compare (DC) submodule of each MCPWM module for actions such as tripzones and syncing. You can set the following parameters for MCPWM:

TZ# MUX select

Select the MUX to map the signal to the MUX output.

Selecting Disable all indicates that all MUXes are disabled and the TRIP X-BAR# is not configured.

This parameter is available for F28E12x processors.

Select MUX input

Select the input to the MUX selected in TZ# MUX select.

Select the input signals for the MUX which is sent to the MCPWM module. You can select one signal per MUX. The input signal to the MUX varies based on the MUX selected and processor.

TZ# MUX (MUX 0->31)

Indicates the input signal selected for each MUX. For example, XXXX1XXXXXXXXXXXXXXXXXXXXXXXXXX indicates that input signal 1 was selected for MUX 4. X indicates that the MUX is disabled and no signal from the MUX will be sent to the MCPWM X-BAR output.

All the signals which are selected will be logically OR'd and sent to the TZ# signal of MCPWM.

Reset TZ# MUX

Resets the signal selection for the MUX done so far.

Resets the TZ# MUX (MUX 0->31) and Select MUX input inputs.

Invert TZ# output

Enable to invert the TZ output signal to the MCPWM.

Timer period units

Select the units for the timer period. Options are Clock cycles or Seconds.

Default clock time period

Specify the default time period for the MCPWM module. When timer period units is set to Clock cycles, the valid range is 0 to 65535. When timer period units is set to Seconds, specify a positive value.

Counting mode

Select the counting mode for the time-base counter. Options are Up or Up-Down.

Time base clock (TBCLK) prescaler divider

Select the prescaler divider for the time-base clock. Available values range from 1 to 32768 in powers of 2.

Active period register load option

Select when to load the active period register from the shadow register. Options are Counter equals to zero, Counter equals to zero or SYNC event, SYNC event, or Immediate without using shadow.

Enable synchronization action

Enable to configure phase synchronization for the MCPWM module.

Default phase offset value

Specify the default phase offset value for the MCPWM module.

Peripheral synchronization selection

Select the peripheral synchronization source for the MCPWM module.

SYNCI Input X-BAR

Select the input X-BAR for SYNCI.

SYNCI pin assignment

Indicates the GPIO pin for the MCPWM external sync input.

SYNCO pin assignment

Assign the MCPWM external sync pulse output (SYNCO) to a GPIO pin.

EXTSYNCOUT source selection

Select the external SYNCOUT source for the MCPWM module.

MCPWMxSYNCIN source selection

Select the MCPWMxSYNCIN source for the synchronization input pulse for the MCPWM module.

PWM#x pin assignment

Assign the GPIO pin to the MCPWM PWM#x module output.

See Also

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