Main Content

Verify Frequency of PLLRAW Clock Using IO Device Builder App

Open Live Script

This example shows how to use the IO Device Builder app to verify the frequency of the PLLRAW clock. This example uses XTAL clock as a reference clock for verifying the frequency. For clock verification, Dual-Clock Comparator Module 0 (DCC0) is utilized.

The DCC module is used in validating the integrity and performance of clock signals within a system.

The XTAL clock, serving as the reference clock at 20MHz, is compared against the PLLRAW clock, which needs to be verified and is expected to operate at 120MHz.

Prerequisites

  • Ensure that C2000Ware is installed as recommended by hardware setup screens for C2000 Microcontroller Blockset.

Note: No circuit connections are required for this example.

Open the IO Device Builder App

To open the IO Device Builder app, perform these steps.

  1. Start MATLAB® and then open / create a Simulink® model.

  2. Go to Modeling > Model Settings to open the Configuration Parameters dialog box.

  3. Open the Hardware Implementation pane, and select a Texas Instruments™ C2000™ board, which supports DCC module . This example uses TI F28003x board.

  4. On the Hardware tab of the Simulink toolstrip, in Prepare section, under Design, choose IO Device Builder.

Select Working Directory and Add Third-party Source Files

Once the Source files location page loads, select the working directory and add third-party source files.

On the Source files location page:

  1. Click Select and select the working directory. In the working directory, the generated system object, along with the corresponding .cpp and .h files, and the model are located.

  2. Click Add folder and add the folders where third-party .c/.h files are present.. Only the files present directly within the selected folder are included, and any files present within subfolders are excluded.

  3. Click Next to continue.

Select Source Files

On the Source files page, select the dcc.c driver file and then click Next to continue.

Specify Block Parameters

On the Block parameters page:

1. Specify the block name and add block description.

2. Add the following mask parameters for the block.

Tunable Parameters: Set the following tunable parameters to allow tuning while the model is running.

  • TestClock: Data type: uint8, Initial value: 0

  • TestClockFrequency: Data type: single, Initial value: 120

  • DccErrorTolerance: Data type: single, Initial value: 1

  • AllowableFrequencyTolerance: Data type: single, Initial value: 0

Non tunable Parameters:

  • DccModuleAddress: Data type: uint32, Initial value: 0

  • ReferenceClock: Data type: uint8, Initial value: 0

  • ReferenceClockFrequency: Data type: single, Initial value: 20

3. Click Next to continue.

Select Outputs for the Block

On the Outputs page:

  1. Add Output port as Status and set data type as uint32 and Dimension as [1,1].

  2. Click Next to continue.

Select Inputs for the Block

On the Inputs page:

  1. Remove inputs for the block, if any already added.

  2. Click Next to continue.

Preview Block

On the Block image page, view the preview of the block with the inputs and outputs you added. Click Next to continue.

Generate System Object Files

On the Generate page, the file generation location is displayed.

Note: Clear the Select to generate a C++ driver option, as C++ is not supported for TI C2000 boards.

Click Generate to generate the system object files.

Next Steps

On the Next Steps page, the files generated are shown and the next steps to be performed are displayed.

Click Finish to complete the process. The generated 'c' file opens automatically.

Perform these steps.

1. Modify the generated .c file as requied by referring to the driver file. A sample generated .c file is shown below.

#include "C:\user\DemoDcc\DccClockVerification.h" //App generated header. Do not modify.
#include "driverlib.h"
#include "device.h"

#define PASS 1
#define FAIL 0

// TestClockFrequency single [1,1] Tunable
// DccErrorTolerance single [1,1] Tunable
// AllowableFrequencyTolerance single [1,1] Tunable
// TestClock uint8 [1,1] Tunable
// DccModuleAddress uint32 [1,1] Non tunable
// ReferenceClock uint8 [1,1] Non tunable
// ReferenceClockFrequency single [1,1] Non tunable

uint32_T  DccModuleAddressParam;
uint8_T  ReferenceClockParam;
float  ReferenceClockFrequencyParam;
void setupFunctionDccClockVerification(float * TestClockFrequency,int size_vector__1,float * DccErrorTolerance,int size_vector__2,float * AllowableFrequencyTolerance,int size_vector__3,
uint8_T * TestClock,int size_vector__4,uint32_T  DccModuleAddress,int size_vector__5,uint8_T  ReferenceClock,int size_vector__6,float  ReferenceClockFrequency,int size_vector__7){
    
DccModuleAddressParam = DccModuleAddress;
    ReferenceClockParam = ReferenceClock;
    ReferenceClockFrequencyParam = ReferenceClockFrequency;

    if (DccModuleAddressParam == 0) {
        DccModuleAddressParam = DCC0_BASE;
    }
    // Check if DccModuleAddressParam is 1 and set it to DCC1_BASE if it is
    else if (DccModuleAddressParam == 1) {
        DccModuleAddressParam = DCC1_BASE;
    }
}

// Status uint32 [1,1]

void stepFunctionDccClockVerification(uint32_T * Status,int size_vector_1, float * TestClockFrequency,int size_vector__1, float * DccErrorTolerance,int size_vector__2, 
float * AllowableFrequencyTolerance,int size_vector__3, uint8_T * TestClock,int size_vector__4){

    bool status=0;
    // Verify the frequency of PLL clock using the XTAL as reference clock
    // FClk1 = PLL frequency = 120MHz
    // FClk0 = XTAL frequency = 20MHz
    // Tolerance = 1%
    // Allowable Frequency Tolerance = 0% (update as per the error in the XTAL frequency)
    // SysClk Freq = 120MHz
    //
    // Note: Update the parameters if you are using different PLL or XTAL frequencies,
    //
    // status = DCC_verifyClockFrequency(DCC0_BASE,
    //                                   DCC_COUNT1SRC_PLL, 120.0F,
    //                                   DCC_COUNT0SRC_XTAL, 20.0F,
    //                                   1.0F, 0.0F, 120.0F);

    status = DCC_verifyClockFrequency(DccModuleAddressParam,
                                      *TestClock, *TestClockFrequency,
                                      ReferenceClockParam, ReferenceClockFrequencyParam,
                                      *DccErrorTolerance, *AllowableFrequencyTolerance, 120.0F);

    //
    // Status of the PLLRAW clock verification
    //
    if (!status)
    {
        *Status = FAIL;
    }
    else
    {
        *Status = PASS;
    }
}

3. Open the generated Simulink model.

4. Add a MATLAB System block and assign the generated system object file without .m extension to the block.

5. Add and connect Display blocks to the output ports.

6. Modify the PLL output divider and System clock divider in the Configuration Parameters pane. To achieve a PLL frequency of 120MHz, set these options.

  • In the Simulink model, navigate to Modeling > Model Settings and in the Configuration Parameters dialog box, click Hardware Implementation > Target hardware resources > Clocking and then modify the PLL output divider and System clock divider as shown in this image.

A sample Simulink model is shown here.

Monitor and Tune the Model

When you perform Monitor and Tune action for the model, the host computer communicates with the target, on which the generated executable runs. To perform Monitor and Tune:

1. In the Simulink model, press Ctrl+E. The Configuration Parameters dialog box appears.

2. Navigate to Code Generation > Optimization and ensure that Tunable is selected for Default parameter behavior.

3. Click Apply and OK.

4. In the Simulink model, click Hardware and click Monitor & Tune. You can observe from the Diagnostic Viewer that the code is generated for the model and the host connects to the target after loading the generated executable.

5. In the Hardware tab, click Stop button to terminate the simulation.

Other Things to Try

  • Create complex device driver blocks such as LIN, Analog subsystem and so on.