Where are Expected Outputs of Test Generation in Simulink Design Verifier?

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Monika Jaskolka 2014-10-1

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https://ww2.mathworks.cn/matlabcentral/answers/157004-where-are-expected-outputs-of-test-generation-in-simulink-design-verifier

评论： Pat Canny 2020-7-30

When performing test generation using SDV, in the options you can checkmark the option to "Include expected output values" of the test cases generated. However, when I inspect the sldvData.mat file, I do not find the expectedOutputs. The dataValues, timeValues, etc. are all found within TestCases. Am I looking in the wrong place or is this a bug? I am using Matlab 2011b.

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Ajay krishna Vasanthakumar 2020-7-28

Hello Monika,

Can u please help me with answers for few questions?

does SDV creates a dynmaic test vector (test value for each step time) or a static one ?
If it creates dynamic test vector how many test vector does it creates?
If the solver is variable step solver what will be the time interval of test value value generation?(like time=[1 2 3],values[4 5 6]).

I will be more happy if i get answer for these questions :)

Thanks

V. Ajay krishna

Pat Canny 2020-7-30

Hi Ajay,

Hopefully I can help:

#1: The test vectors generated by Simulink Design Verifier are meant to be simulated within Simulink. I assume this is what you mean by "dynamic".

#2: The number of test vectors generated depends on the number of objectives for which Simulink Design Verifier is trying to generate tests and the current tool configuration. In most cases, the tool will try to generate as few tests as possible to achieve the coverage objectives. However, you can modify this behavior by selecting a different 'TestSuiteOptimization' in sldvoptions . If this is set to 'IndividualObjectives', Design Verifier will generate a test case for each objective. If this is set to 'LongTestCases', Design Verifier will try to generate longer test cases to achieve more coverage objectives for a given test case. We generally recommend users start with the "Auto" setting for 'TestSuiteOptimization'.

#3: Simulink Design Verifier does not support variable step solvers. The solver must be Fixed-step: https://www.mathworks.com/help/sldv/ug/check-model-compatibility.html

Thanks.

- Pat

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Answer 1

Monika Jaskolka 2020-3-2

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https://ww2.mathworks.cn/matlabcentral/answers/157004-where-are-expected-outputs-of-test-generation-in-simulink-design-verifier#answer_418129

This is a bug. I could not find a workaround other than to upgrade to a newer version of Matlab.

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Pat Canny 2020-3-6

编辑：Pat Canny 2020-3-6

Hi Monika,

Sorry this question went unaddressed for so long! We have deliberately tried to do better in responding to MATLAB Answers more promptly in recent months. "SLDV MATLAB Answers Under New Management"

I realize this is an older question, but just to confirm your workflow (I'll use a shipping example; using R2019b):

open_system 'sldvdemo_cruise_control';
opts = sldvoptions;
opts.Mode = 'TestGeneration';
opts.ModelCoverageObjectives = 'MCDC';
opts.SaveExpectedOutput = 'on';
[ status, files ] = sldvrun('sldvdemo_cruise_control', opts, true);
load(files.DataFile) % loads sldvData from .mat file to workspace
% Plot expectedOuputs from first generated test case
timeValues_first_test = sldvData.TestCases(1).timeValues;
expectedOutputs_first_test = sldvData.TestCases(1).expectedOutput; % creates 2x1 cell array. Model has two outputs.
figure
plot(timeValues_first_test,expectedOutputs_first_test{1})
hold on
plot(timeValues_first_test,expectedOutputs_first_test{2})