Is it possible for Filter Design HDL coder to generate a FIR filter whose sampling rate is higher than clock rate?

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Tong Xu
Tong Xu 2018-10-16
评论： Tong Xu 2018-10-22
Hi everyone,
I'm using the Filter Design HDL coder in Matalb 2018b. Since our ADC has a much higher sampling rate than the FPGA clock rate, I want to generate a FIR filter which supports parallel processing. This kind of FIR filter is named super sampling rate FIR filter. I checked the User Guide of Filter Design HDL Coder but I can't find a solution. The fully parallel architecture described in the User Guide only supports one sample per clock period. Is it possible generate super sampling rate FIR filter using Filter Design HDL Coder? Is there any examples?
I want to generate DA-based FIR filter, I'm wondering if it supports super sampling rate FIR filter.
Thank you.
Regards, Tong

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Bharath Venkataraman
编辑：Bharath Venkataraman 2018-10-18
This is available with HDL Coder and the FIR block in DSP System Toolbox. Please take a look at this example to see how it works.
This page describes the various blocks that support super sampling/high throughput algorithms.
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Bharath Venkataraman
Bharath Venkataraman 2018-10-21
It appears that your product installation may be corrupted. Would you be able to install the product again and see if this issue still occurs?

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