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Kiran Kintali


Last seen: 3 days ago

MathWorks

145 total contributions since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

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Answered
stateflow hdl code generation hierachy flatten
This is a good suggestion. Unfortunately it is not currently possible to reduce the depth of logical paths during codegeneration...

4 days ago | 0

Answered
How to serialize an HDL Coder function with a vector input ?
You can use mlhdlc_heq.m and mlhdlc_heq_tb.m example files on how to serialize input passed to the design. Thanks. https://www....

5 days ago | 0

| accepted

Answered
[HDL Coder] How to keep subsystems port names when applying input/output pipelining
Hi, Can you share the model and generated code? Thanks.

13 days ago | 0

Answered
Trigger type 'either' is not supported for HDL code generation.
This is a known limitation with HDL code generation. Stateflow team at MathWorks has provided a modeling workaround. Please see ...

15 days ago | 0

| accepted

Answered
Trigger type 'either' is not supported for HDL code generation.
Can you share a sample model of your Stateflow usecase? Thanks

17 days ago | 0

Answered
When using the HDL Workflow Advisor, why do I get errors in Task 1.2 that mention "Dot indexing is not support for variables of this type"?
Thanks for identifying the root cause of the issue. It is worth improving the error message. I do not see a model. Can you creat...

1 month ago | 0

Answered
how do i get the hdl code from simulink with sine waves in my model
Hi Shaurya, Can you check these options? https://www.mathworks.com/help/hdlcoder/ref/sinehdloptimized.html https://www.mathw...

1 month ago | 1

Answered
Rate transitions and HDL generation port requirement
hi michael, can you share the model to further understand the behavior? thanks

1 month ago | 0

Answered
how do i get the hdl code from simulink with sine waves in my model
Hi Shaurya, Can you share the model? Thanks.

1 month ago | 0

Answered
generic port length when integrating existing HDL code with Simulink model
Can you share a model to describe your usecase? please also attach generated code and expected code with the blackbox settings u...

1 month ago | 0

Answered
Check Block Compatibiity Error
Can you share a sample model? Thanks

1 month ago | 0

Answered
generic port length when integrating existing HDL code with Simulink model
Have you used the GenericList parameter in HDLCoder? Thanks GenericList Pass a cell array variable that contains cell arr...

1 month ago | 0

Answered
Unable to find the software for XILINXLOGICORE
It is possible Xilinx LOGICORE is not avaialble with Vivado and you need to setup Xilinx ISE to use it. Please check Xilinx Docu...

2 months ago | 1

| accepted

Answered
Unable to find the software for XILINXLOGICORE
hi Samuel, There is a special Note about Vivado in the help text: Please note that Xilinx Vivado launcher for Windows i...

2 months ago | 1

Answered
How to use Matlab generated c code for High Level Synthesis ?
Hi Shravan, I believe you are generating C code from MATLAB code using MATLAB Coder and trying it to take it through GAUT - Hig...

2 months ago | 0

Answered
HDL Workflow Advisor change the name of the generated header file
This header file has the same name as the IP core. The IP core name can be set in Task 3.2 “Generate RTL Code and IP Core”. C...

2 months ago | 0

| accepted

Answered
Error: A cast between fixpt and floating point type is not supported
Hi Sandip, Since dwt2 is not supported out of the box, please consider using core MATLAB to HDL features and implement dwt2_fp...

2 months ago | 1

Answered
Error: A cast between fixpt and floating point type is not supported
Hi Sandip, The issue here is not related to fixed-point conversion; HDL Coder currently does not support dwt2 function out of t...

2 months ago | 0

| accepted

Answered
Matlab HDL coder can not perform to send an image matrix to a matlab function.How to resolve it?
https://www.mathworks.com/help/hdlcoder/examples/image-enhancement-by-histogram-equalization.html 'mlhdlc_heq.m' (DUT) and 'mlh...

2 months ago | 1

| accepted

Answered
VHDL code generation and avoiding magic numbers?
Currently HDLCoder does not have the capaibility of generating all constants into pkg file. Please reach out to support@mathwork...

3 months ago | 0

Answered
Delay balancing unsuccessful because Signal rate of value inf found.
Can you share the model and the version of MATLAB you are using that exhibits this behavior? Thanks.

3 months ago | 0

Answered
Delay balancing unsuccessful because Signal rate of value inf found.
Can you run HDL model advisor check shown below to see if you can detect the block? If the block with Inf sample time is not...

3 months ago | 0

Answered
How to convert a Simscape Electrical model into a Fixed-point HDL generable model ?
This workflow currently supports double, single and in future half precision formats. The workflow currently does not yet supp...

3 months ago | 1

| accepted

Answered
can a single model containing 2 different subsystems generate HDL and C code for the subsystems seperately?
Yes. You can generate code independently using embedded Coder and HDL Coder products for the two subsystems and integrate the co...

4 months ago | 1

Answered
HDL Coder to / downto order
This is a limitation due to an early decision made to emit vector of boolean to use 'TO' syntax and is not currently customizabl...

4 months ago | 0

| accepted

Answered
pir_core:pirudd:assertionFailed: Assertion failed: b:\matlab\src\cgir_hdl\dom_pir_core\cgtransformdriver.cpp:155:lsv_result != CG::transform::StructExplosion::RESULT_ERROR
This looks like an unexpected internal error. Can you contact techsupport@mathworks.com with reproduction steps? Thanks

5 months ago | 0

Answered
HDL Coder 'abs' : Double and complex data types not supported.
This is currently a limitation on the Abs block. https://www.mathworks.com/help/simulink/slref/mathfunction.html In the interi...

5 months ago | 0

Answered
Getting timing closure for HDL Coder IP with multicycle paths
Please contact support@mathworks.com for help on this topic. Can you share the Simulink model with us to better answer the quest...

5 months ago | 0

| accepted

Answered
Why do I receive an assertion in portmgr.cpp:340:Error: Invalid port index 13 requested when 12 is the max port index for comp
Thank you. Great to know you found a reasonable workaround for the issue. If you can still share the reproduction steps for the...

6 months ago | 0

Answered
Why do I receive an assertion in portmgr.cpp:340:Error: Invalid port index 13 requested when 12 is the max port index for comp
This is not expected and you are run into an internal error. Can you submit reproduction steps to support@mathworks.com? than...

6 months ago | 0

| accepted

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