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Deep Learning HDL Toolbox - HDL generation
https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html Deep ...

3 years 前 | 0

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E310/HDL Coder - How can I design a model where the ARM application individually requests frames of samples from the E310 Receiver/FPGA?
HW/SW Codesign workflow of SDR algorithms for USRP™ embedded series radio hardware This guide helps you to deploy partitioned...

3 years 前 | 0

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How to convert the Simulink project to VHDL code?
Implement Digital Downconverter for FPGA This example shows how to design a digital downconverter (DDC) for radio communication...

3 years 前 | 0

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MATLAB stuck when HDL coder converted the model to Verilog
Can you share your model or reach out to tech support for further guidance on the topic? In general this model seems to be usin...

3 years 前 | 0

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Compiling fixedpt converted code into VHDL
https://www.mathworks.com/help/hdlcoder/gs/generate-hdl-code-from-matlab-code-using-the-command-line-interface.html Generate HD...

3 years 前 | 0

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HDL coder error,Call to function 'fmod' is not supported for HDL code generation,
This message scenerio happens when HDL Coder finds an unsupported function error. Can you share a sample MATLAB code and Testb...

3 years 前 | 0

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In Simulink HDLcoder, which converts a model into a hardware description language, it's stuck in this interface
I wonder if the model has unsupported constructs for HDL Code Generation. However you should recieve an early warning about the ...

3 years 前 | 0

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HDL Coder Example for ZedBoard
Can you review this shipping example? It should be customizable for your usecase. Generate IP Core from MATLAB for Blinking LED...

3 years 前 | 0

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How to create a custom fpga board to use with IP core generation
An example of an FPGA board which does not contain a processor can be found here: Working with an FPGA Board Using IP Core Gen...

3 years 前 | 0

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why the subtraction gives the wrong ans.?
Integers in MATLAB have Saturation behaviors. To avoid saturation behavior of Integers when using MATLAB Code, you may need to ...

3 years 前 | 0

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What exactly do coder config InputPipeline and OutputPipeline do?
In MATLAB to HDL workflow InputPipeline and OutputPipeline options insert pipelines on the whole function. You can also control...

3 years 前 | 1

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Problem facing in matlab code to vhdl code convertion
https://www.mathworks.com/help/hdlcoder/matlab-algorithm-design.html Please check out this page for best practices in writing M...

3 years 前 | 0

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hdlcoder.optimizeDesign on matlab function
hdlcoder.optimizeDesign runs Simulink to HDL workflow (makehdl) under the hood. I have communicated to the dev team the request...

3 years 前 | 0

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Simulink HDL coder Shift register SIPO
https://www.mathworks.com/help/hdlcoder/ref/deserializer1d.html You can also consider using the Deserializer block to convert s...

3 years 前 | 1

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Is it possible to use different target hardware for implementing deep learning HDL toolbox?
DL HDL ships bitstreams for few reference boards. However, DL HDL IP can be customized to any custom FPGA / ASIC configuration....

3 years 前 | 1

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why do i get this error?
Please attach files that can run without error. I got an error running the runtrial.m file. You need break the design that nee...

3 years 前 | 0

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why do i get this error?
Can you share the design, testbench and the project files? It looks like you are running into some issue with classes during f...

3 years 前 | 0

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HDLCoder hdl.ram: Error System Object methods can only be called once
can you please share the design.m, testbench.m and matched_filter.prj files associated with the matched filter design with the c...

3 years 前 | 0

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Error while using HDL coder: variable-size matrix type is not supported for HDL code generation
Can you please share design (Inter_func.m) and testbench (Inter_func_tb.m) driving the design with valid inputs and the HDL Code...

3 years 前 | 0

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How to solve error Qt: Untested Windows version 6.2 detected! while trying to run create project task in hdl coder ?
Can you share few more details and the error stack you see in the command window? Does this error happen when running AMD/Xil...

3 years 前 | 0

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Error while targeting FPGA through simulink, I am trying to implement 'OFDM Transmit and Receive Using Analog Devices AD9361/AD9364' example of MATLAB.
I think you are referring to this demo. OFDM Transmit and Receive Using Analog Devices AD9361/AD9364 https://www.mathworks.c...

3 years 前 | 0

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how do i convert this code to HDL using hdl coder?
You can follow these examples in Deep Learning HDL Toolbox. https://www.mathworks.com/help/deep-learning-hdl/examples.html

3 years 前 | 0

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Meaning code setDatType RefMdl
This code is looking for specific block name patterns and based on block name assigning output types for the blocks.

3 years 前 | 0

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[Simulink] get the parameter of the block to be variable in HDL
HDL Coder supports bitshift block with shift length specified via input port. Reach out to technical support on your specific u...

3 years 前 | 0

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While running the 'OFDM Transmit and Receive Using Analog Devices AD9361/AD9364' example of MATLAB in Ubuntu, Matlab is crashing while generating the bitstream in HDL Workflow
This is not exected behavior. Can you share more details? Does the folder have HDL code generated? What is the last phase wher...

3 years 前 | 0

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Binary Point scaling Vs Slope Bias scaling
HDL Coder currently does not support Slope Bias Scaling for efficiency reasons. Please consider using Binary Point Scaling for b...

3 years 前 | 0

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HDL coder implementation of dsp.MovingAverage (moving/block average)
function [y, validOut] = moving_average(x, validIn) %#codegen % Declare persistent array and persistent window size persist...

3 years 前 | 0

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HDL FIFO accepts three more pushes before signalling full
Can you share the model? thanks

3 years 前 | 0

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How to create or develop an HDL Verifier function for a specific HDL model
https://www.mathworks.com/help/hdlcoder/ug/verify-sobel-edge-detection-algorithm-in-matlab-to-hdl-workflow.html Example that sh...

3 years 前 | 0

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HDL Coder fails to generate VHDL, Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\corecomplowering.hpp:97
This is an unexpected error. Can you file a bug report with the support team? There should be a readable error message in case ...

3 years 前 | 0