Validation Shift-Left: Enabling Early SerDes Mixed-Signal Validation

Modern mixed-signal ASIC designs, such as SerDes, face increasing complexity due to the intricate interaction between analog and digital subsystems and the challenges of advanced silicon processes. This complexity extends design times and introduces uncertainty, particularly as analog design often lags behind digital, delaying overall validation. Typically, system models aid in defining architecture and exploring design space, with analog specifications derived from these models. The paper proposes a method to automatically generate SystemVerilog models for analog components from these system models, integrating them with digital functionality to create configurable analog models. This approach allows for early validation by shifting the effort left in the workflow, using models based on initial design explorations. As designs evolve and simulation data becomes available, system models can be refined to align with actual analog behavior, enabling continuous updates of SystemVerilog models. The paper demonstrates this workflow using a SerDes analog block, specifically a continuous-time linear equalizer (CTLE), beginning with a model based on the 802.3ck reference and refining it with simulation data to ensure accuracy throughout the project lifecycle.

This paper was presented at DesignCon 2022.