Airbus Designs Onboard FPGA-Based Deep Learning Processor Using MATLAB
Processor Met Requirements for Throughput and Power Consumption When Tested Against Anomalies Detected on Operational Satellites
“The MATLAB deep learning processor IP core is essentially platform-agnostic, which allowed for its incorporation into a real-time operating system that could be certified for space. A major challenge was to develop an application that interacted with it, but MathWorks support helped us a lot in this.”
Key Outcomes
- Developed workflow based on MATLAB for rapid prototyping and verification of deep neural networks on FPGAs, enabling collaboration between hardware, systems, and deep learning engineers
- Detected potential satellite failure modes earlier compared to traditional thresholding-based methods
- Produced deep learning processor for use and deployment with any FPGA vendor with FreeRTOS or other operating systems
- Deep learning models can be updated onboard without the need for FPGA reprogramming
Real-world anomalies detected by the deep learning network running on an FPGA.
Modern space vehicles must continuously monitor telemetry data and detect or predict any anomalous behavior in sensor data. Traditional methods, such as threshold-based monitoring, struggle with the task due to the high dimensionality and quantity of data received from onboard sensors. The highly dynamic environment of an orbiting satellite also makes it challenging to identify anomaly indicators.
To overcome these challenges, Airbus Defence and Space GmbH decided to implement deep learning models for anomaly detection by developing an onboard system for fault detection, isolation, and recovery (FDIR).
Airbus has found FPGAs to be an ideal platform for onboard spacecraft systems because of their high performance and long life. FPGAs are reprogrammable, can be made to tolerate space radiation, and can be designed to consume small amounts of power. However, implementing deep learning models for time-critical tasks of this scope using resource-limited FPGAs can be a significant challenge.
The Airbus design team opted to use Deep Learning HDL Toolbox™ to generate a MATLAB® deep learning processor IP core as an AI accelerator. The workflow supported use of FreeRTOS™ as the operating system. For testing, Airbus used an AMD® Zynq™ UltraScale+™ MPSoC ZCU102 board together with a long short-term memory (LSTM) model, which was trained on a set of related telemetry parameters. Furthermore, updates to the LSTM models did not require the FPGA to be reprogrammed as only the updated model needed to be compiled and downloaded into the deep learning processor again.
The LSTM models trained in TensorFlow™ were imported into MATLAB. Based on those models, the deep learning processor configuration was optimized for performance and resource usage. After this, the deep learning processor IP core was generated as synthesizable, target-independent HDL code using HDL Coder™, and integrated into the Airbus reference design via AXI interfaces. The engineers then used a Python®-based workflow to program the deep learning processor and trigger it from the Arm® processor on the AMD Zynq MPSoC.
When testing the FDIR system on the hardware board against anomalies detected on operational satellites, the deep learning processor worked reliably while meeting requirements for throughput and power consumption. Airbus plans to deploy an FPGA-based FDIR system on future spacecraft.
Products Used
Related Resources
