Deep Learning HDL Toolbox provides functions and tools to prototype and implement deep learning networks on FPGAs and SoCs. It provides pre-built bitstreams for running a variety of deep learning networks on supported AMD® and Altera® FPGA and SoC devices. Profiling and estimation tools let you customize a deep learning network by exploring design, performance, and resource utilization tradeoffs.
Deep Learning HDL Toolbox enables you to customize the hardware implementation of your deep learning network and generate portable, synthesizable Verilog®, SystemVerilog, and VHDL® code for deployment on any FPGA or SoC (with HDL Coder and Simulink).
Using an FPGA Based Deep Learning Processor
The toolbox includes a deep learning processor featuring generic deep learning layers controlled by scheduling logic. This processor performs FPGA-based inferencing of networks using Deep Learning Toolbox.
Compiling and Deploying Networks
Compile a deep learning network into a set of instructions to be run by the deep learning processor. Deploy your network to the FPGA and run prediction while capturing actual on-device performance metrics.
Getting Started with Prebuilt Bitstreams
Rapidly prototype a long short-term memory (LSTM) network using available pre-built bitstreams. Customize bitstream configuration to meet resource use requirements.
Deploying Networks to FPGAs
Use Deep Learning Toolbox to develop RNN and CNN networks or import a network. Then program an FPGA using the deploy command, deploying to AMD or Altera FPGAs.
Running FPGA-Based Inferencing in MATLAB Applications
Run a complete application in MATLAB, including your test bench, preprocessing and post-processing algorithms, and the FPGA-based deep learning inferencing. A single MATLAB command, predict, performs the inferencing on the FPGA and returns results to the workspace in MATLAB.
Profiling FPGA Inferencing and Tuning Network Designs
Using the profile metrics, tune your network configuration by measuring layer-level latency as you run predictions on the FPGA to find performance bottlenecks.
Compressing Deep Learning Network for FPGA Deployment
Reduce resource utilization by compressing your deep learning network with quantization and pruning. Analyze tradeoffs between accuracy and resource utilization using the Model Quantization Library support package.
Customizing the Deep Learning Processor Configuration
Specify hardware architecture options for implementing the deep learning processor, such as the number of parallel threads or maximum layer size.
Generating Synthesizable RTL and IP Cores
Use HDL Coder to generate synthesizable RTL from the deep learning processor. Generate IP core with standard AXI interfaces for integration into AMD and Altera SoC designs.
Product Resources:
Deep Learning HDL Toolbox FAQs
Deep Learning HDL Toolbox provides functions and tools to prototype and implement deep learning networks on FPGAs and SoCs, offering pre-built bitstreams for running networks on supported AMD and Altera devices.
The toolbox supports AMD and Altera FPGA and SoC devices with pre-built bitstreams available for deployment.
Yes, you can program an FPGA using the `deploy` command and run inferencing with a single MATLAB `predict` command, without writing HDL code directly.
You can specify hardware architecture options such as the number of parallel threads or maximum layer size, and use profiling tools to explore design, performance, and resource utilization tradeoffs.
Yes, with HDL Coder and Simulink, you can generate portable, synthesizable Verilog, SystemVerilog, and VHDL code, as well as IP cores with standard AXI interfaces for SoC integration.
Quantization is optional but can reduce resource utilization. You can compress networks using pruning, projection and quantization with the Deep Learning Toolbox Model Compression Library support package.
You can use the profiling tools to capture actual on-device performance metrics, measure layer-level latency, and identify performance bottlenecks while running predictions on the FPGA.
You can deploy CNN and RNN networks, including LSTM networks, developed in Deep Learning Toolbox or imported from other sources.
