Deep Learning HDL Toolbox provides functions and tools to prototype and implement deep learning networks on FPGAs and SoCs. It provides pre-built bitstreams for running a variety of deep learning networks on supported AMD® and Intel® FPGA and SoC devices. Profiling and estimation tools let you customize a deep learning network by exploring design, performance, and resource utilization tradeoffs.
Deep Learning HDL Toolbox enables you to customize the hardware implementation of your deep learning network and generate portable, synthesizable Verilog®, SystemVerilog, and VHDL® code for deployment on any FPGA or SoC (with HDL Coder and Simulink).
Using an FPGA Based Deep Learning Processor
The toolbox includes a deep learning processor featuring generic deep learning layers controlled by scheduling logic. This processor performs FPGA-based inferencing of networks using Deep Learning Toolbox.
Compiling and Deploying Networks
Compile a deep learning network into a set of instructions to be run by the deep learning processor. Deploy your network to the FPGA and run prediction while capturing actual on-device performance metrics.
Getting Started with Prebuilt Bitstreams
Rapidly prototype a long short-term memory (LSTM) network using available pre-built bitstreams. Customize bitstream configuration to meet resource use requirements.
Deploying Networks to FPGAs
Use Deep Learning Toolbox to develop RNN and CNN networks or import a network. Then program an FPGA using the deploy command, deploying to AMD or Intel FPGAs.
Running FPGA-Based Inferencing in MATLAB Applications
Run a complete application in MATLAB, including your test bench, preprocessing and post-processing algorithms, and the FPGA-based deep learning inferencing. A single MATLAB command, predict, performs the inferencing on the FPGA and returns results to the workspace in MATLAB.
Profiling FPGA Inferencing and Tuning Network Designs
Using the profile metrics, tune your network configuration by measuring layer-level latency as you run predictions on the FPGA to find performance bottlenecks.
Compressing Deep Learning Network for FPGA Deployment
Reduce resource utilization by compressing your deep learning network with quantization and pruning. Analyze tradeoffs between accuracy and resource utilization using the Model Quantization Library support package.
Customizing the Deep Learning Processor Configuration
Specify hardware architecture options for implementing the deep learning processor, such as the number of parallel threads or maximum layer size.
Generating Synthesizable RTL and IP Cores
Use HDL Coder to generate synthesizable RTL from the deep learning processor. Generate IP core with standard AXI interfaces for integration into AMD and Intel SoC designs.
