AMD FPGA and SoC Support from HDL Verifier

Debug and test HDL code on AMD FPGAs and SoCs Devices.

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HDL Verifier automates the verification of HDL code on AMD FPGA and SoC Boards by enabling hardware debugging and verification features.

FIL testing helps ensure that the MATLAB algorithm or Simulink design behaves as expected in the real world, increasing confidence in your implementation on an AMD device. The MATLAB algorithm or Simulink model is used to drive FPGA input stimuli and to analyze the output of the FPGA. With FIL testing, you can verify your design at FPGA speeds, enabling you to run more extensive sets of test cases and perform regression tests on your design.

Use FPGA Data Capture to observe signals from your design while the design is running on the AMD FPGA or SoC. You can specify trigger conditions to capture a window of signal data from the FPGA and return the data to MATLAB^® or Simulink for viewing and analysis.

Use AXI Manager to access subordinate memory locations on the board. You can read from and write to on-board memory locations from MATLAB or Simulink over Ethernet to Arm^® cores or programmable logic, or via JTAG, PCI Express^®, or USB Ethernet interface.

The HDL Verifier Support Package for AMD FPGA and SoC Devices supports a wide range of predefined boards from AMD and other suppliers, and you can add additional boards through FPGA Board Customization.