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QSPI Controller Peripheral Configuration

Map QSPI controller peripherals in the Infineon AURIX model to peripheral registers in the MCU

Since R2024a

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Description

View and edit the map of peripherals in the Infineon® AURIX™ model to the hardware peripherals.

Using the Peripheral Configuration tool, you can:

  • View and edit configuration parameters for QSPI controller block.

  • Configure the global parameters. To set the group peripheral, select peripheral in Browser > Peripherals > QSPI Controller . For more, see Map Tasks and Peripherals Using Hardware Mapping.

  • Check for any conflicts between peripherals.

QSPI controller HM

Open the QSPI Controller Peripheral Configuration

  • In the Simulink toolstrip, go to Hardware tab and click Hardware Mapping.

    Hardware Mapping

Parameters

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Global parameters > Module # > Events

Enables the QSPI transmit FIFO interrupt.

When you select this option, the dialog box displays the Tx FIFO Mode Selection options.

Note

Enabling this parameter, expect that the data is handled through interrupts. Therefore it is mandatory to use QSPI Peripheral block (Transfer mode as SPI Transmit) or QSPI Controller (Transfer mode as SPI Transmit or SPI Transmit and Receive) block during the events.

This parameter is read-only.

Select one of these operation modes for Tx FIFO buffer:

  • Single Move — Select this mode to generate an interrupt to refill the transmit buffer as soon as there is a free element.

  • Batch Move — Select this mode to generate an interrupt if the FIFO level of Tx data exceeds above programmed threshold.

Dependencies

To enable this parameter, select the Enable Tx FIFO event parameter.

Specify FIFO level for Tx FIFO event.

Dependencies

To enable this parameter, select the Enable Tx FIFO event parameter.

Enables the QSPI receive FIFO interrupt.

When you select this option, the dialog box displays the Rx FIFO Mode Selection options.

Note

Enabling this parameter, expect that the data is handled through interrupts. Therefore it is mandatory to use QSPI Peripheral block (Transfer mode as SPI Receive) or QSPI Controller block (Transfer mode as SPI Receive or SPI Transmit and Receive) during the events.

This parameter is read-only.

Select one of these operation modes for receive buffer:

  • Single Move — Select this mode to generate an interrupt to fetch the received element as soon as possible.

  • Batch Move — Select this mode to generate an interrupt if the filling level rises above the programmed threshold.

Dependencies

To enable this parameter, select the RxFifo event parameter.

Specify FIFO level for Rx FIFO event.

Dependencies

To enable this parameter, select the Enable Rx FIFO event parameter.

Enables the QSPI error interrupt.

Note

Enabling this parameter, expects that the data is handled through interrupts. Therefore it is recommended to use QSPI block (SPI receive or transmit as transfer mode) during the events.

Global parameters > Module # > Pin selection

Select the QSPI serial clock pin selection. The available pin numbers vary based on the module selected.

Select the QSPI serial data out pin selection. The available pin numbers vary based on the module selected.

Select the QSPI serial data input pin selection. The available pin numbers vary based on the module selected.

Global parameters > Module # > Common pin properties

Select input pull for QSPI pin.

Select drive strength for output pin.

Select the pin speed for QSPI.

Select voltage level of QSPI pin.

Module

Select the QSPI controller module 0 through 4 on the hardware board.

Tx mode

Select the QSPI transmit mode.

  • Continuous - This option activates the chip select signal till the data transfer completes.

  • Single-transfer - This option deactivates the chip select signal for every data element involved in the data transfer.

Clock

Specifies the rate of data communication between the peripherals connected (clock period).

Select the QSPI data heading in binary numbers.

  • MSB first - the bit furthest to the left (msb) is moved first from SDO pin followed by the subsequent left bits.

  • LSB first - the bit furthest to the right (lsb) is moved first from SDO pin followed by the subsequent right bits.

Select the QSPI clock polarity in idle state.

Select the QSPI clock phase.

Enables the QSPI clock parity.

When you select the Enable parity parameter, the dialog box displays the Parity parameter.

Select the QSPI clock parity.

Dependencies

To enable Parity parameter, select the Enable parity parameter.

Enable to configure the QSPI Controller block to either transmit or receive data at a time. Disable to use for both transmit and receive at a time.

Chip Select (CS)

Select the QSPI chip select pin.

Select the QSPI chip select active level.

CS timing parameters in clock ticks

Introduces the selected delay between the active edge of the CS pin and the first shift clock edge.

Introduces the selected delay between shift clock period of a data block and is followed either by the deactivating edge of CS pin, or a new data block in continuous mode.

Introduces the selected delay between the end of the last trail phase of a frame.

Version History

Introduced in R2024a

See Also

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