Channel 0 – Channel 15
R2026bSet ADC sample state count for individual channels 0 through 15
Since R2026b
Model Configuration Pane: Hardware Implementation / Embedded Coder Hardware Support Package / Hardware board settings / Target hardware resources / ADC
Description
Specify the number of sampling clock cycles for the ADC sample-and-hold phase for each individual channel (Channel 0 through Channel 15). A higher value increases the sampling time, which can improve conversion accuracy for high-impedance analog sources.
Each channel has its own field, allowing you to configure different sample state counts for different channels based on source impedance requirements.
Dependencies
To enable these parameters, select the Set sample state counts of channels parameter.
Settings
7
(default)Specify a positive integer value representing the number of sampling clock cycles.
Recommended Settings
No recommendation.
Programmatic Use
| No programmatic use is available. |
Version History
Introduced in R2026b
