Exp HDL Optimized

R2026b

Compute base-e exponential of input

Since R2026b

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  • Exp HDL Optimized block

Libraries:
Fixed-Point Designer HDL Support / Logic and Bit Operations

Description

The Exp HDL Optimized block computes the base-e exponential of an input. This block is optimized for efficient HDL code generation with HDL Coder™.

Ports

Input

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Value to compute base-e exponential of, specified as a real-valued scalar. Fixed-point inputs must use binary-point scaling.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Whether input is valid, specified as a Boolean scalar. This control signal indicates when the data from the u input port is valid. When this value is 1 (true), the block captures the value at the u input port. When this value is 0 (false), the block ignores the input samples.

Data Types: Boolean

Output

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Base-e exponential of input, returned as a scalar.

Dependencies

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Whether output data is valid, returned as a Boolean scalar. When the value of this control signal is 1 (true), the block has successfully computed the output. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

Parameters

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To edit block parameters interactively, use the Property Inspector. From the Simulink® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

Data type of the output y, specified as a Simulink.NumericType object, numerictype object, workspace variable, or MATLAB expression. Fixed-point data types must use binary-point scaling.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter: OutDataType
Values: fixdt(0,16,12) (default) | Simulink.NumericType object | numerictype object | workspace variable | MATLAB expression

Algorithms

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Extended Capabilities

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C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2026b

See Also

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