Extract MSB

R2026b

Extract most significant bit (MSB) of input

Since R2026b

Libraries:
Fixed-Point Designer HDL Support / Logic and Bit Operations

Description

The Extract MSB block allows you to extract the most significant bit (MSB) from the stored integer value of the input signal. For a signed input, the Extract MSB block returns the sign bit. If the input is a built-in integer or fixed-point data type, the output is returned as a ufix1 type. Floating-point inputs are passed through the block unchanged.

Examples

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Extract Most Significant Bit from Stored Integer Value

Open Live Script

This example shows how to extract the most significant bit (MSB) from the stored integer value of an input signal.

Open and simulate the model.

open_system('ex_extract_msb_block');

Ports

Input

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u — Input signal
scalar | vector | matrix | N-D array

Input signal, specified as a scalar, vector, matrix, or N-D array. Floating-point inputs are passed through the block unchanged.

Output

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y — Extracted most significant bit
scalar | vector | matrix | N-D array

Extracted most significant bit, returned as a scalar, vector, matrix, or N-D array. For a signed input, the Extract MSB block returns the sign bit. If the input u is a built-in integer or fixed-point data type, the output y is returned as a ufix1 type. Floating-point inputs are passed through the block unchanged.

See Fixed-Point Numbers in Simulink for an explanation of fixed-point data type and scaling notation in Simulink^®.

Data Types: single | double | fixed point
Complex Number Support: Yes

Extended Capabilities

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C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is `0`. For more details, see OutputPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

Limitations

N-D array is not supported for HDL code generation.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2026b

Extract MSB

Description

Examples

Extract Most Significant Bit from Stored Integer Value

Ports

Input

u — Input signal
scalar | vector | matrix | N-D array

Output

y — Extracted most significant bit
scalar | vector | matrix | N-D array

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Blocks

Functions

Extract MSB

Description

Examples

Extract Most Significant Bit from Stored Integer Value

Ports

Input

u — Input signal scalar | vector | matrix | N-D array

Output

y — Extracted most significant bit scalar | vector | matrix | N-D array

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Blocks

Functions

u — Input signal
scalar | vector | matrix | N-D array

y — Extracted most significant bit
scalar | vector | matrix | N-D array

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.