Preserve Bus structure in the generated HDL code

R2026b

Generate code with VHDL record or SystemVerilog structure types

Since R2022b

Model Configuration Pane: Global Settings / Coding style

Description

Note

From R2026b, this parameter is not available in the HDL Code Generation model configuration parameter pane. You can configure this parameter programmatically by using hdlset_param or makehdl functions.

Generate code with VHDL® record or SystemVerilog structure types for bus signals at design-under-test (DUT) interfaces and different subsystem-level interfaces. For more information, see Generate HDL Code with Record or Structure Types for Bus Signals.

Dependencies

To enable this parameter, set Target language to VHDL or SystemVerilog.

Settings

on (default) | off

Default: On

on

Generate record or structure types for bus signals in your HDL code. For example, this code snippet shows the generated VHDL code for a subsystem where In1 and Out1 are the bus ports that are defined using the record types. 

ENTITY Subsystem IS
  PORT( clk          :   IN    std_logic;
        reset        :   IN    std_logic;
        In1          :   IN    BusObject_record;  -- record {double,double}
        Out1         :   OUT   BusObject_record  -- record {double,double}
        );
END Subsystem;
The package file defines the record BusObject_record, which consists of two bus elements with data type double.

PACKAGE Subsystem_pkg IS
  TYPE BusObject_record IS RECORD
    signal1           : std_logic_vector(63 DOWNTO 0);
    signal2           : std_logic_vector(63 DOWNTO 0);
  END RECORD BusObject_record;

END Subsystem_pkg;

off

HDL Coder™ flattens the bus elements ports at the subsystem interface. This code snippet shows the generated VHDL code for the subsystem without record types:

ENTITY Subsystem IS
  PORT( clk              :   IN    std_logic;
        reset            :   IN    std_logic;
        In1_signal1      :   IN    std_logic_vector(63 DOWNTO 0);  -- double
        In1_signal2      :   IN    std_logic_vector(63 DOWNTO 0);  -- double
        Out1_signal1     :   OUT   std_logic_vector(63 DOWNTO 0);  -- double
        Out1_signal2     :   OUT   std_logic_vector(63 DOWNTO 0)  -- double
        );
END Subsystem;

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: GenerateRecordType
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2022b

expand all

See Also