Input clock frequency, specified as a scalar. In a PLL system, the clk in port is connected to the output port of a VCO block.

Data Types: double

Ratio of output to input clock frequency, specified as a fractional scalar.

The value at the div-by port is split into two parts: the integer part (N) and the fractional part (.FF).

Data Types: double

Output clock frequency, specified as a scalar. In a PLL system, the clk out port is connected to the feedback input port of a PFD block. The output at the clk out port is a square pulse train of 1 V amplitude.

Data Types: double

The fractional missing pulse storage. The value of the state port goes up by F with each rising edge of the clk out value of the previous cycle. Whenever the state port value goes over 1, the value overflows and sets the carry port value to 1.

Data Types: double

Output port that activates the pulse swallow function when state port overflows. The pulse removal is analogous to dividing the input frequency by N+1 instead of N.

Data Types: Boolean

Select to enable increased buffer size during simulation. This increases the buffer size of the Logic Decision inside the Fractional Clock Divider with Accumulator block. By default, this option is deselected.

Number of samples of the input buffering available during simulation, specified as a positive integer scalar. This sets the buffer size of the Logic Decision inside the Fractional Clock Divider with Accumulator block.

Selecting different simulation solver or sampling strategies can change the number of input samples needed to produce an accurate output sample. Set the Buffer size to a large enough value so that the input buffer contains all the input samples required.

Dependencies

This parameter is only available when Enable increased buffer size option is selected in the Block Parameters dialog box.

Programmatic Use