Fractional Clock Divider with Accumulator

Clock divider that divides frequency of input signal by fractional number

Library:
Mixed-Signal Blockset / PLL / Building Blocks

Description

The Fractional Clock Divider with Accumulator block divides the frequency of the input signal by a tunable fractional value (N.FF). When compared to the Single Modulus Prescaler block, the Fractional Clock Divider with Accumulator block helps to achieve a narrow channel spacing that can be less than the reference frequency of a phase-locked loop (PLL) system.

Ports

Input

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`clk in` — Input clock frequency
scalar

Input clock frequency, specified as a scalar. In a PLL system, the clk in port is connected to the output port of a VCO block.

Data Types: double

`div-by` — Ratio of output to input clock frequency
fractional scalar

Ratio of output to input clock frequency, specified as a fractional scalar.

The value at the div-by port is split into two parts: the integer part (N) and the fractional part (.FF).

Data Types: double

Output

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`clk out` — Output clock frequency
scalar

Output clock frequency, specified as a scalar. In a PLL system, the clk out port is connected to the feedback input port of a PFD block. The output at the clk out port is a square pulse train of 1 V amplitude.

Data Types: double

`state` — Missing fractional pulse storage
scalar

The fractional missing pulse storage. The value of the state port goes up by F with each rising edge of the clk out value of the previous cycle. Whenever the state port value goes over 1, the value overflows and sets the carry port value to 1.

Data Types: double

`carry` — Activates the pulse swallow function when state port overflows
`0` (default) | `1`

Output port that activates the pulse swallow function when state port overflows. The pulse removal is analogous to dividing the input frequency by N+1 instead of N.

Data Types: Boolean

Parameters

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`Enable increased buffer size` — Enable increased buffer size
off (default) | on

Select to enable increased buffer size during simulation. This increases the buffer size of the Logic Decision inside the Fractional Clock Divider with Accumulator block. By default, this option is deselected.

`Buffer size` — Number of samples of the input buffering available during simulation
`1` (default) | positive integer scalar

Number of samples of the input buffering available during simulation, specified as a positive integer scalar. This sets the buffer size of the Logic Decision inside the Fractional Clock Divider with Accumulator block.

Selecting different simulation solver or sampling strategies can change the number of input samples needed to produce an accurate output sample. Set the Buffer size to a large enough value so that the input buffer contains all the input samples required.

Dependencies

This parameter is only available when Enable increased buffer size option is selected in the Block Parameters dialog box.

Programmatic Use

Use get_param(gcb,'NBuffer') to view the current value of Buffer size.
Use set_param(gcb,'NBuffer',value) to set Buffer size to a specific value.

Model Examples

Frequency Division Using Fractional Clock Divider with Accumulator

Open the model fractionalClockDivider_w_Accumulator. The model consists of a Pulse Generator and a Fractional Clock Divider with Accumulator block.

More About

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Inside the Mask

The Fractional Clock Divider with Accumulator consists of three subsystems: a Fractional Accumulator, a Pulse Swallower, and a Single Modulus Prescaler block.

When the block first receives an input signal, the Single Modulus Prescaler block divides the input signal by the integer part (N) of the value of the div-by port. The fractional part (.FF) is stored in the state port of the Fractional Accumulator subsystem.

The Fractional Accumulator subsystem updates the state port value with each rising edge received by the clk out port in the previous cycle. When the value of the state port goes over 1, the value overflows and changes the value emitted by the carry port to 1.

The carry port activates the Pulse Swallower subsystem, and removes one pulse from the clk in signal. It is like dividing the input signal by a factor of N+1, achieving the overall fractional division.