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Phase-Locked Loops

Design and simulate analog phase-locked loop (PLL) systems

Design a PLL system starting from basic foundation blocks or from a family of reference architectures. Simulate and analyze the PLL system to verify key performance metrics until you meet the system specifications.

You can start by providing the specifications and impairments of each foundation block and connect the blocks to model different PLL architectural models (bottom-up approach). Alternatively, you can start from complete system-level models of typical PLL architectures and customize those models until to meet your system specifications (top-down approach).

Use Measurements and Testbenches throughout the design process to verify the specifications of the blocks and of the entire system in presence of imperfections.


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Charge PumpOutput a current proportional to the difference in duty cycle between two input ports
Loop FilterModel second-, third-, or fourth-order passive loop filter
PFDPhase/frequency detector that compares phase and frequency between two signals
VCOModel voltage controlled oscillator
Ring Oscillator VCOModel ring oscillator VCO
Single Modulus PrescalerInteger clock divider that divides frequency of input signal
Dual Modulus PrescalerInteger clock divider with two divider ratios
Fractional Clock Divider with AccumulatorClock divider that divides frequency of input signal by fractional number
Fractional Clock Divider with DSMDelta Sigma Modulator based fractional clock divider
Fractional N PLL with AccumulatorFrequency synthesizer with accumulator based fractional N PLL architecture
Fractional N PLL with Delta Sigma ModulatorFrequency synthesizer with delta sigma modulator based fractional N PLL architecture
Integer N PLL with Dual Modulus PrescalerFrequency synthesizer with dual modulus prescaler based integer N PLL architecture
Integer N PLL with Single Modulus PrescalerFrequency synthesizer with single modulus prescaler based integer N PLL architecture


Design and Evaluate Simple PLL Model

This example shows how to design a simple phase-locked loop (PLL) using a reference architecture and validate it using PLL Testbench.

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