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Simulink 模块注意事项

名称、数学运算、端口和子系统、信号路由、逻辑和位运算

建模规范

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hisl_0031: Model file names
hisl_0032: Model element names
hisl_0001: Usage of Abs block
hisl_0002: Usage of remainder and reciprocal operations
hisl_0003: Usage of square root operations
hisl_0028: Usage of Reciprocal Square Root blocks
hisl_0004: Usage of natural logarithm and base 10 logarithm operations
hisl_0005: Usage of Product blocks
hisl_0029: Usage of Assignment blocks
hisl_0066: Usage of Gain blocks
hisl_0067: Protect against divide-by-zero calculations
hisl_0006: Usage of While Iterator blocks
hisl_0007: Usage of For Iterator or While Iterator subsystems
hisl_0008: Usage of For Iterator Blocks
hisl_0010: Usage of If blocks and If Action Subsystem blocks
hisl_0011: Usage of Switch Case blocks and Action Subsystem blocks
hisl_0024: Inport interface definition
hisl_0025: Design min/max specification of input interfaces
hisl_0026: Design min/max specification of output interfaces
hisl_0077: Outport interface definition
hisl_0078: Usage of identical modeling patterns
hisl_0079: Connections to root input/output ports
hisl_0015: Usage of Merge blocks
hisl_0021: Consistent vector indexing method
hisl_0022: Data type selection for index signals
hisl_0023: Verification of variant blocks
hisl_0034: Usage of Signal Routing blocks
hisl_0016: Usage of blocks that compute relational operators
hisl_0017: Usage of blocks that compute relational operators (2)
hisl_0018: Usage of Logical Operator block
hisl_0019: Usage of bitwise operations
hisl_0033: Usage of Lookup Table blocks
hisl_0072: Usage of tunable parameters for referenced models
hisl_0073: Usage of bit-shift operations