Detect Decrease

Detect decrease in signal value

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Libraries:
Simulink / Logic and Bit Operations
HDL Coder / Logic and Bit Operations

Description

The Detect Decrease block determines if an input is strictly less than its previous value.

This block supports only discrete sample times.

Examples

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Detect Decreasing Signal Values

Open Model

This example shows how to determine if an input signal is strictly less than its previous value using the Detect Decrease block. When the current input to the Detect Decrease block is less than its previous value, the block outputs one (true). When the current input is greater than or equal to the previous signal value, the Detect Decrease block outputs zero (false).

Ports

Input

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Port_1 — Input signal
scalar | vector | matrix

Input signal, specified as a scalar, vector, or matrix.

Output

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Port_1 — Output signal
0 | 1

Output signal, true (equal to 1) when the input signal is less than its previous value; false (equal to 0) when the input signal is greater than or equal to its previous value.

Parameters

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Initial condition — Initial condition for the previous input
0 (default) | scalar | vector

Set the initial condition for the previous input U/z.

Programmatic Use

Block Parameter: vinit

Type: character vector

Values: scalar | vector

Default: '0'

Input processing — Specify sample- or frame-based processing
`Elements as channels (sample based)` (default) | `Columns as channels (frame based)`

Specify whether the block performs sample- or frame-based processing:

Columns as channels (frame based) — Treat each column of the input as a separate channel (frame-based processing).
Note
Frame-based processing requires a DSP System Toolbox™ license.
For more information, see Sample- and Frame-Based Concepts (DSP System Toolbox).
Elements as channels (sample based) — Treat each element of the input as a separate channel (sample-based processing).

Use Input processing to specify whether the block performs sample- or frame-based processing. For more information about these two processing modes, see Sample- and Frame-Based Concepts (DSP System Toolbox).

Programmatic Use

Block Parameter: InputProcessing

Type: character vector

Values:

'Columns as channels
                        (frame based)'

'Elements as channels (sample
                        based)'

Default:

'Elements as channels
                        (sample based)'

Output data type — Data type of the output
`boolean` (default) | `uint8`

Set the output data type to boolean or uint8.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'boolean' | 'uint8'

Default: 'boolean'

Block Characteristics

Data Types	`Boolean` \| `double` \| `enumerated` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Generated code relies on memcpy or memset functions (string.h) under certain conditions.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

Detect Decrease

Description

Examples

Detect Decreasing Signal Values

Ports

Input

Port_1 — Input signal scalar | vector | matrix

Output

Port_1 — Output signal 0 | 1

Parameters

Initial condition — Initial condition for the previous input 0 (default) | scalar | vector

Programmatic Use

Input processing — Specify sample- or frame-based processing Elements as channels (sample based) (default) | Columns as channels (frame based)

Programmatic Use

Output data type — Data type of the output boolean (default) | uint8

Programmatic Use

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Port_1 — Input signal
scalar | vector | matrix

Port_1 — Output signal
0 | 1

Initial condition — Initial condition for the previous input
0 (default) | scalar | vector

Input processing — Specify sample- or frame-based processing
`Elements as channels (sample based)` (default) | `Columns as channels (frame based)`

Output data type — Data type of the output
`boolean` (default) | `uint8`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.