If

Select subsystem execution using logic similar to if-else statement

Libraries:
Simulink / Ports & Subsystems

Description

The If block, along with If Action Subsystem blocks that contain an Action Port block, implements if-else logic to control subsystem execution. For an example that uses the If block, see Select Subsystem Execution.

Model ex_if_block

Examples

Simulink Subsystem Semantics

This set of examples shows different types of Simulink® Subsystems and what semantics are used when simulating these subsystems. Each example provides a description of the model and the subtleties governing how the model is executed.

Open Live Script

If-Then-Else Blocks

The effect of feeding a sine wave into If Action Subsystem blocks. It is designed to illustrate the similarity between the If Action Subsystem block and the Enabled Subsystem block.

Open Model

Modeling Clutch Lock-Up Using If Blocks

Use If/Else subsystems to build a clutch model. An 'If' subsystem models the clutch dynamics in the locked position while an 'Else' subsystem models the unlocked position. One or the other is enabled using the 'If' block. The dot-dashed lines from the 'If' block denote control signals, which are used to enable If/Else (or other conditional) subsystems. Checking any of the boxes on the GUI produces a plot of any of the selected variables (versus time).

Open Model

Limitations

The If block has the following limitations:

It does not support tunable parameters. Values for an if or elseif expression cannot be tuned during a simulation in normal or accelerator mode, or when running generated code.
To implement tunable if-else expressions, tune the expression outside the If block. For example, use the Relational Operator block to evaluate the expression outside of the If block or add the tunable parameter as an input to the If block.
It does not support custom storage classes. See Organize Parameter Data into a Structure by Using Struct Storage Class (Embedded Coder).
The If expression and Elseif expressions cannot accept certain operators, such as +, -, *, and /.

Ports

Input

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Logical operands — Values for evaluating logical expressions
scalar | vector

Inputs u1,u2,...,un must have the same data type. The inputs cannot be of any user-defined type, such as an enumerated type.

The If block does not directly support fixed-point data types. However, you can use the Compare To Constant block to work around this limitation. See Support for Fixed-Point Data Type in Select Subsystem Execution.

Output

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Action — Action signal for an If Action Subsystem block
scalar

Outputs from the if, else, and elseif ports are action signals to If Action Subsystem blocks.

Parameters

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Number of inputs — Specify number of input ports
`1` (default) | integer

1: Specify one input port.
integer: Specify the number of input ports. Block ports are labeled with a 'u' character followed by a number, 1,2,...,n, where n equals the number of inputs that you specify.

Programmatic Use

Block Parameter: NumInputs

Type: character vector

Values: '1' | integer in quotes

Default: '1'

If expression — Specify logical expression
`u1 > 0` (default) | logical expression

The If Action Subsystem attached to the if port executes when its associated expression evaluates to true.

u1 > 0

Specify sending an action signal on the output port when the input u1 is greater than 0.

logical expression

Specify logical expression. This expression appears on the If block adjacent to the if output port.

The expression can include only the operators <, <=, ==, ~=, >, >=, &, |, ~, (), unary-minus. Operators such as +, -, *, /, and ^ are not allowed. The expression must not contain data type expressions, for example, int8(6), and must not reference workspace variables whose data type is other than double or single.

Programmatic Use

Block Parameter: IfExpression

Type: character vector

Values: 'u1 > 0' | logical expression in quotes

Default: 'u1 > 0'

Elseif expressions — Specify logical expression
empty (default) | list of logical expressions

The If Action Subsystem attached to an elseif port executes when its expression evaluates to true and all if and elseif expressions are false.

empty

Logical expressions not specified.

list of logical expressions

Specify a list of logical expressions delimited by commas. The expressions appear on the If block below the if port and above the else port when you select the Show else condition check box.

Expressions can include only the operators <, <=, ==, ~=, >, >=, &, |, ~, (), unary-minus. Operators such as +, -, *, /, and ^ are not allowed. The expressions must not contain data type expressions, for example, int8(6), and must not reference workspace variables whose data type is other than double or single.

Programmatic Use

Block Parameter: ElseIfExpressions

Type: character vector

Values: '' | list of logical expressions in quotes

Default: ''

Show else condition — Control display of else port
`on` (default) | `off`

When the if port and all elseif port expressions are false, the else port sends an action signal to execute the attached If Action Subsystem block.

on: Display else port.
off: Hide else port.

Programmatic Use

Block Parameter: ShowElse

Type: character vector

Values: 'on' | 'off'

Default: 'on'

Enable zero-crossing detection — Control zero-crossing detection
`on` (default) | `off`

Control zero-crossing detection.

on: Detect zero crossings.
off: Do not detect zero crossings.

Programmatic Use

Block Parameter: ZeroCross

Type: character vector

Values: 'on' | 'off'

Default: 'on'

Block Characteristics

Data Types	`Boolean` \| `double` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`no`
Variable-Size Signals	`no`
Zero-Crossing Detection	`yes`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced before R2006a

If

Description