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Dead Logic Detection

Dead logic detection identifies decision coverage and condition coverage outcomes that cannot occur. In some cases dead logic arises due to errors within your designs. Before you simulate a model, use dead logic detection to analyze the model for dead logic. In Simulink® Design Verifier™, design error detection for dead logic consists of two analysis options:

  • Dead logic (partial): If you select this option, Simulink Design Verifier analyzes your model without making any approximations, such as rational approximation for floating points, or while loop approximation. For more information, see Role of Approximations During Model Analysis. With this option, Simulink Design Verifier does not report active logic or undecided objectives and it may not identify some dead logic in your model.

    This option is available in:

  • Run exhaustive analysis: With this option, Simulink Design Verifier reports active logic in addition to dead logic as well as undecided objectives. This option may in some cases identify or find additional dead logic. The analysis may use approximations and are reported accordingly.

    This option is available in Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane.

Run a Partial Check for Dead Logic

If you are not using the Model Advisor, to detect dead logic:

  1. On the Design Verifier tab, in the Mode section, select Design Error Detection.

  2. Click Error Detection Settings.

  3. In the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane:

    1. Enable the Dead logic (partial) option.

    2. Clear the Run exhaustive analysis option, if it is selected.

    3. Set Coverage objectives to be analyzed to MCDC. The available options from the drop-down menu are Decision, Condition Decision, and MCDC.

  4. To apply these settings, click OK and close the Configuration Parameters window.

  5. Click Detect Design Errors.

Run an Exhaustive Analysis for Dead Logic

  1. On the Design Verifier tab, in the Mode section, select Design Error Detection.

  2. Click Error Detection Settings.

  3. In the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane:

    1. Enable the Dead logic (partial) option.

    2. Select the Run exhaustive analysis option.

    3. Set Coverage objectives to be analyzed to MCDC. The available options from the drop-down menu are Decision, Condition Decision, and MCDC.

  4. To apply these settings, click OK and close the Configuration Parameters dialog box.

  5. Click Detect Design Errors.

Run a Dead Logic Analysis and Review Results

This example shows how to detect dead logic in the sldvSlicerdemo_dead_logic example model. Dead logic detection finds the unreachable objectives in the model that cause the model element to remain inactive.

  1. Open the sldvSlicerdemo_dead_logic model.

    openExample('slcheck/AnalyzeTheDeadLogicExample',...
'supportingFile','sldvSlicerdemo_dead_logic');

  2. On the Design Verifier tab, in the Mode section, select Design Error Detection.

  3. Click Error Detection Settings.

  4. In the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane:

    1. Enable the Dead logic (partial) option.

    2. Clear the Run exhaustive analysis option, if it is selected.

    3. Set Coverage objectives to be analyzed to MCDC. The available options from the drop-down menu are Decision, Condition Decision, and MCDC.

  5. Click Detect Design Errors.

    The software analyzes the model for dead logic and displays the results in the Results Summary window. The result indicates that 10 of the 32 objectives were found to be dead logic.

    Results summary window that shows design error detection analysis results.

  6. Click Highlight analysis results on model. The dead logic model elements are highlighted in red.

  7. Open the Controller subsystem, and click the OR block highlighted in red. The Result Inspector displays the summary of the dead logic.

    The set input is equal to 1, so the input port 1 of the OR block can only be true. The status implies that the input port 1 false condition is a dead logic. Similarly, the input port 2 is unreachable, as the objective never executes and is dead logic.

    Results for OR block in the Result Inspector showing dead logic.

  8. To view the detailed analysis report, in the Results Summary window, click HTML.

    The report displays the summary of all the results that are dead logic in the model.

    Dead Logic

    Report for dead logic in the model that shows the type of objective, model item, and description.

    The software stores the detailed analysis results in the DeadLogic field in the Manage Simulink Design Verifier Data Files. You can use the data file for further analysis of the results.

Suggestion:

You can use Model Slicer to find the parameters which could have an impact on a particular block by following these steps:

a. Create an object of SLSlicerAPI.ParameterDependence using Model Slicer.

slicerObj = slslicer('sldvSlicerdemo_dead_logic');
pd = slicerObj.parameterDependence;

b. Find the parameters affecting the Discrete-Time Integrator block.

param = parametersAffectingBlock(pd, 'sldvSlicerdemo_dead_logic/Controller/PI Controller/Discrete-Time Integrator');

The image above displays the parameters returned by the function parametersAffectingBlock which have an impact on the Discrete-Time Integrator block. The parameters returned by the function can be considered for tuning.

c. Perform clean-up to exit compile state of the model.

slicerObj.terminate;

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