External Memory Access
R2026bConnect your IP design to programmable logic (PL) double data rate 4 (DDR4) memory by using AXI4-Master interfaces. Capture analog-to-digital converter (ADC) data from PL-DDR4 memory and transmit waveforms through the digital-to-analog converter (DAC) using data read from PL-DDR4 memory.
Topics
- Reference Designs for RFSoC Devices
Learn about how to use RFSoC reference designs and their requirements.
Featured Examples
ADC Data Capture to DDR Memory on RFSoC Device
Perform analog-to-digital converter (ADC) data captures with programmable logic (PL) double data rate 4 (DDR4) memory.
DAC Data Transmit from DDR Memory on RFSoC Device
Transmit waveforms out of the digital-to-analog converter (DAC) that is read from programmable logic (PL) double data rate 4 (DDR4) memory. Using PL-DDR4 memory offers advantages such as the ability to access 4 gigabytes of memory space. This amount of memory can help facilitate applications requiring large waveform transmissions that are not normally feasible with FPGA block random access memory (BRAM). This figure shows the relevant intellectual property (IP) interfaces and connectivity that are used in this design.
