|Show in SDI||Show task execution data collected on hardware in Simulation Data Inspector.|
|Save to file||Save task execution data to a file.|
|Overwrite file||Overwrite last task execution data file.|
|Instrumentation||Choose to perform code instrumentation or kernel Instrumentation.|
Simulated kernel latency delay.
|Set seed for simulating task duration and memory access||Set random number generator seed.|
|Seed Value||Seed for the simulation of task duration deviation.|
|Cache input data at task start||Cache input data at task start.|
|Number of cores||Set the number of CPU cores in the processor.|
|View/Edit Memory Map|
Choose whether to perform global synthesis or per IP core synthesis.
|Include a JTAG master for host-based interaction|
Use host-based scripts with an integrated JTAG master on the target platform.
|Include processing system|
For processor-based platforms, include the processing system.
|Interrupt latency (s)|
The latency from hardware asserting an interrupt to the start of the interrupt service routine.
|Register configuration clock frequency (MHz)|
The system configuration clock drives the configuration register interfaces for the vendor IP cores in the system.
|IP core clock frequency (MHz)|
The clock for all Simulink® based generated HDL IP cores.
|Controller clock frequency (MHz)|
Frequency of datapath between memory interconnect and memory controller.
|Controller data width (bits)|
Bit width of datapath between memory interconnect and memory controller.
|Bandwidth derating (%)|
For every 100 clocks, will hold off all transaction execution for this number of clocks.
|First write transfer latency (clocks)|
Number of clock cycles between write request and start of transfer.
|Last write transfer latency (clocks)|
Number of clock cycles between the end of write transfer and completion of transaction.
|First read transfer latency (clocks)|
Number of clock cycles between read request and start of transfer.
|Last read transfer latency (clocks)|
Number of clock cycles between the end of read transfer and completion of transaction.
|Interconnect clock frequency (MHz)|
Frequency of the master datapath to the interconnect controller in MHz.
|Interconnect data width (bits)|
Data width of master datapath to interconnect controller in bits.
|Interconnect FIFO depth (num bursts)|
Maximum number of bursts that can be buffered before data is dropped.
|Interconnect almost-full depth|
When the almost full depth is reached, the attached channel protocol interface block asserts back pressure to the data source.
|Memory channel diagnostic level|
The internal operation of the memory channel can be instrumented for debug or diagnostic analysis.
|Include AXI interconnect monitor|
Gather performance metrics of the memory interconnect such as data throughput, latency, and number of bursts executed.
|Trace capture depth||Maximum number of Trace entries to be logged in trace mode|